View M58LT128GST1ZA5E_2883963.PDF datasheet online --- IC-ON-LINE

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preliminary data this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. rev 1.0 september 2005 1/98 1 m58lt128gst m58lt128gsb 128mbit (8mb x16, multiple bank, multi-level, burst) 1.8v supply secure flash memories features summary supply voltage ?v dd = 1.7 to 2.0v for program, erase and read ?v ddq = 2.7 to 3.6v for i/o buffers ?v pp = 9v for fast program synchronous / asynchronous read ? random access: 110ns ? asynchronous page read: 25ns. ? synchronous burst read: 52mhz synchronous burst read suspend programming time ? 10s typical word program time using buffer enhanced factory program command memory organization ? multiple bank memory array: 8 mbit banks ? parameter blocks (top or bottom location) dual operations ? program/erase in one bank while read in others ? no delay between read and write operations hardware protection ? all blocks write protected when v pp v pplk security ? software security features ? 64-bit unique device identifier ? 2112 bits of user-programmable otp memory common flash interface (cfi) 100,000 program/erase cycles per block electronic signature ? manufacturer code: 20h ? device code: m58lt128gst: 88c6h m58lt128gsb: 88c7h ecopack ? package available bga tbga64 (za) 10 x 13mm www.st.com
m58lt128gst, m58lt128gsb 2/98 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 address inputs (a0-a22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 data input/output (dq0-dq15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 chip enable (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 output enable (g) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 write enable (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6 reset (rp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.7 latch enable (l) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.8 clock (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.9 wait (wait) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.10 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.10.1 v ddq supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.11 v pp program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.12 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.13 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 address latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 read array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
m58lt128gst, m58lt128gsb 3/98 4.6 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.7 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.8 buffer program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.9 buffer enhanced factory program command . . . . . . . . . . . . . . . . . . . . . . . . 23 4.9.1 setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.9.2 program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.9.3 exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.10 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.11 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.11.1 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.12 set configuration register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 program/erase controller status bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2 erase suspend status bit (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.3 erase status bit (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4 program status bit (sr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5 v pp status bit (sr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.6 program suspend status bit (sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.7 bank write/multiple word program status bit (sr0) . . . . . . . . . . . . . . . . . . 33 6 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.1 read select bit (cr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2 x-latency bits (cr13-cr11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.3 wait polarity bit (cr10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.4 data output configuration bit (cr9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5 wait configuration bit (cr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.6 burst type bit (cr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.7 valid clock edge bit (cr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.8 wrap burst bit (cr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.9 burst length bits (cr2-cr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1 asynchronous read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1.1 asynchronous random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
m58lt128gst, m58lt128gsb 4/98 7.1.2 asynchronous page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2 synchronous burst read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2.1 synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2.2 single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8 dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . . . 45 9 program and erase times and endurance cycles . . . . . . . . . . . . . . . . . . 47 10 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 appendix a block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 appendix b common flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 appendix c flowcharts and pseudo codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 appendix d command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
m58lt128gst, m58lt128gsb 5/98 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 4. command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 6. factory program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 7. electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8. protection register lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 10. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 11. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 12. wait at the boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 13. dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 14. dual operations allowed in same bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 15. dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 16. program/erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 17. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 18. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 19. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 20. dc characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 21. dc characteristics - voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 22. asynchronous read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 23. synchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 24. write ac characteristics, write enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 25. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 26. reset and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 27. tbga64 10x13mm - 8x8 active ball array, 1mm pitch, package mechanical data . . . . . . 66 table 28. ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 29. daisy chain ordering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 30. m58lt128gst - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 31. m58lt128gst - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 32. m58lt128gst - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 33. m58lt128gsb - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 34. m58lt128gsb- main bank base addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 35. m58lt128gsb - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 36. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 37. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 38. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 39. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 40. primary algorithm-specific extended query table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 41. protection register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 42. burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 43. bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 44. bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 45. bank and erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 46. command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 47. command interface states - modify table, next output state. . . . . . . . . . . . . . . . . . . . . . 92 table 48. command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
m58lt128gst, m58lt128gsb 6/98 table 49. command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . 95 table 50. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
m58lt128gst, m58lt128gsb 7/98 list of figures figure 1. logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. tbga64 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. protection register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 5. x-latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 6. wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 7. ac measurement i/o waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 figure 8. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 9. asynchronous random access read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 10. asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 11. synchronous burst read ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 12. single synchronous read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 13. synchronous burst read suspend ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 14. clock input ac waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 15. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 16. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 17. reset and power-up ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 18. tbga64 10x13mm - 8x8 active ball array, 1mm pitch, bottom view package outline . . . 66 figure 19. program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 20. buffer program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 21. program suspend & resume flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . 85 figure 22. block erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 23. erase suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 24. protection register program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 25. buffer enhanced factory program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . 89
1 summary description m58lt128gst, m58lt128gsb 8/98 1 summary description the m58lt128gst and m58lt128gsb are 128 mbit (8 mbit x16) non-volatile secure flash memories. the devices may be erased electrically at block level and programmed in-system on a word-by- word basis using a 1.7 to 2.0v v dd supply for the circuitry and a 2.7 to 3.6v v ddq supply for the input/output pins. an optional 9v v pp power supply is provided to speed up factory programming. the devices feature an asymmetrical block architecture and are based on a multi-level cell technology. the memory array is organized as 131 blocks, and is divided into 8 mbit banks. there are 15 banks each containing 8 main blocks of 64 kwords, and one parameter bank containing 4 parameter blocks of 16 kwords and 7 main blocks of 64 kwords. the multiple bank architecture allows dual operations, while programming or erasing in one bank, read operations are possible in other banks. only one bank at a time is allowed to be in program or erase mode. it is possible to perform burst reads that cross bank boundaries. the bank architecture is summarized in ta bl e 2 , and the memory maps are shown in figure 3 . the parameter blocks are located at the top of the memory address space for the m58lt128gst, and at the bottom for the m58lt128gsb. each block can be erased separately. erase can be suspended, in order to perform a program or read operation in any other block, and then resumed. program can be suspended to read data at any memory location except for the one being programmed, and then resumed. each block can be programmed and erased over 100,000 cycles using the supply voltage v dd . there is a buffer enhanced factory programming command available to speed up programming. program and erase commands are written to the command interface of the memory. an internal program/erase controller takes care of the timings necessary for program and erase operations. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec standards. the device supports synchronous burst read and asynchronous read and page read from all blocks of the memory array; at power-up the device is configured for asynchronous read. in synchronous burst read mode, data is output on each clock cycle at frequencies of up to 52mhz. the synchronous burst read operation can be suspended and resumed. the device features an automatic standby mode. when the bus is inactive during asynchronous read operations, the device automatically switches to the automatic standby mode. in this condition the power consumption is reduced to the standby value and the outputs are still driven. the m58lt128gst and m58lt128gsb are equipped with several features to increase data protection: hardware protection: all blocks are protected from program and erase operations when the v pp v pplk . a full set of software security features described in a dedicated application note. please contact stmicroelectronics for further details. 64-bit unique device identifier 2112 bits of user-programmable otp memory
m58lt128gst, m58lt128gsb 1 summary description 9/98 the device includes 17 protection registers and 2 protection register locks, one for the first protection register and the other for the 16 one-time-programmable (otp) protection registers of 128 bits each. the first protection register is divided into two segments: a 64 bit segment containing a unique device number written by st, and a 64 bit segment one-time- programmable (otp) by the user. the user programmable segment can be permanently protected. figure 4 shows the protection register memory map. the devices are offered in tbga64 10 x 13mm, 1mm pitch. in order to meet environmental requirements, st offers the m58lt128gst and m58lt128gsb in ecopack ? package. ecopack package is lead-free. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. the memories are supplied with all the bits erased (set to ?1?). figure 1. logic diagram ai10259b a0-a22 w dq0-dq15 v dd m58lt128gsb m58lt128gst e v ss 16 g rp v ddq v pp l k wait v ssq
1 summary description m58lt128gst, m58lt128gsb 10/98 table 1. signal names a0-a22 address inputs dq0-dq15 data input/outputs, command inputs e chip enable g output enable w write enable rp reset kclock l latch enable wait wait v dd supply voltage v ddq supply voltage for input/output buffers v pp optional supply voltage for fast program & erase and write protect v ss ground v ssq ground input/output supply nc not connected internally
m58lt128gst, m58lt128gsb 1 summary description 11/98 figure 2. tbga64 connections (top view through package) table 2. bank architecture number bank size parameter blocks main blocks parameter bank 8 mbits 4 blocks of 16 kwords 7 blocks of 64 kwords bank 1 8 mbits - 8 blocks of 64 kwords bank 2 8 mbits - 8 blocks of 64 kwords bank 3 8 mbits - 8 blocks of 64 kwords ---- ---- ---- ---- bank 14 8 mbits - 8 blocks of 64 kwords bank 15 8 mbits - 8 blocks of 64 kwords ai10270b dq6 a0 v ssq v dd dq10 v dd dq7 dq5 v ddq dq2 h dq14 v ss dq13 d a15 a19 e a8 c a16 a20 a10 a14 k a7 b a18 a1 a12 a13 a 8 7 6 5 4 3 2 1 a6 a2 a3 a4 g f e dq0 a5 v pp a17 a9 a11 rp dq15 dq9 dq8 dq1 dq4 dq3 g dq12 dq11 w v ss nc nc nc nc nc nc nc nc nc a21 a22 wait nc nc l
1 summary description m58lt128gst, m58lt128gsb 12/98 figure 3. memory map ai10261 m58lt128gst - top boot block address lines a22-a0 8 main blocks bank 15 m58lt128gsb - bottom boot block address lines a22-a0 64 kword 000000h 00ffffh 64 kword 070000h 07ffffh 64 kword 600000h 60ffffh 64 kword 670000h 67ffffh 64 kword 680000h 68ffffh 64 kword 6f0000h 6fffffh 64 kword 700000h 70ffffh 64 kword 770000h 77ffffh 64 kword 780000h 78ffffh 64 kword 7e0000h 7effffh 16 kword 7f0000h 7f3fffh 16 kword 7fc000h 7fffffh 4 parameter blocks parameter bank parameter bank 16 kword 000000h 003fffh 16 kword 00c000h 00ffffh 64 kword 010000h 01ffffh 64 kword 070000h 07ffffh 64 kword 080000h 08ffffh 64 kword 0f0000h 0fffffh 64 kword 100000h 10ffffh 64 kword 170000h 17ffffh 64 kword 180000h 18ffffh 64 kword 1f0000h 1fffffh 64 kword 780000h 78ffffh 64 kword 7f0000h 7fffffh bank 3 bank 2 bank 1 bank 15 bank 3 bank 2 bank 1 8 main blocks 8 main blocks 8 main blocks 7 main blocks 4 parameter blocks 7 main blocks 8 main blocks 8 main blocks 8 main blocks 8 main blocks
m58lt128gst, m58lt128gsb 2 signal descriptions 13/98 2 signal descriptions see figure 1: logic diagram and table 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a22) the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. 2.2 data input/output (dq0-dq15) the data i/o output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation. 2.3 chip enable (e ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is at v il and reset is at v ih the device is in active mode. when chip enable is at v ih the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. 2.4 output enable (g ) the output enable input controls data outputs during the bus read operation of the memory. 2.5 write enable (w ) the write enable input controls the bus write operation of the memory?s command interface. the data and address inputs are latched on the rising edge of chip enable or write enable whichever occurs first. 2.6 reset (rp ) the reset input provides a hardware reset of the memory. when reset is at v il , the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the reset supply current i dd2 . refer to table 20: dc characteristics - currents , for the value of i dd2. after reset all blocks are in the protected state and the configuration register is reset. when reset is at v ih , the device is in normal operation. exiting reset mode the device enters asynchronous read mode, but a negative transition of chip enable or latch enable is required to ensure valid data outputs. the reset pin can be interfaced with 3v logic without any additional circuitry. it can be tied to v rph (refer to table 21: dc characteristics - voltages ).
2 signal descriptions m58lt128gst, m58lt128gsb 14/98 2.7 latch enable (l ) latch enable latches the a0-a22 address bits on its rising edge. the address latch is transparent when latch enable is at v il and it is inhibited when latch enable is at v ih . 2.8 clock (k) the clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a clock edge (rising or falling, according to the configuration settings) when latch enable is at v il . clock is ignored during asynchronous read and in write operations. 2.9 wait (wait) wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. this output is high impedance when chip enable is at v ih or reset is at v il . it can be configured to be active during the wait cycle or one clock cycle in advance. the wait signal is forced deasserted when output enable is at v ih . 2.10 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). 2.10.1 v ddq supply voltage v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently from v dd . v ddq can be tied to v dd or can use a separate supply. 2.11 v pp program supply voltage the v pp pin is both a power supply and a write protect pin. the functions are selected by the voltage range applied to the pin. when v pp is lower than v pplk , it is seen as a write protect pin protecting the whole memory array. program and erase operations on all blocks are ignored while v pp is low. when v pp is higher than v pp1 , the memory reverts to the previous protection state of the memory array. program and erase operations can now modify the data in any block (refer to table 21: dc characteristics - voltages for v pplk and v pp1 values). v pp is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. if v pp is in the range of v pph it acts as a power supply pin. in this condition v pp must be stable until the program/erase algorithm is completed. the v pp pin must not be left floating or unconnected or the device may become unreliable. a 0.1f capacitor should be connected between the v pp pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during unlock bypass program, i pp .
m58lt128gst, m58lt128gsb 2 signal descriptions 15/98 2.12 v ss ground v ss ground is the reference for the core supply. it must be connected to the system ground. 2.13 v ssq ground v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss note: each device in a system should have v dd , v ddq and v pp decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). see figure 8: ac measurement load circuit . the pcb track widths should be sufficient to carry the required v pp program and erase currents.
3 bus operations m58lt128gst, m58lt128gsb 16/98 3 bus operations there are six standard bus operations that control the device. these are bus read, bus write, address latch, output disable, standby and reset. see table 3: bus operations , for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus write operations. 3.1 bus read bus read operations are used to output the contents of the memory array, the electronic signature, the status register and the common flash interface. both chip enable and output enable must be at v il in order to perform a read operation. the chip enable input should be used to enable the device. output enable should be used to gate data onto the output. the data read depends on the previous command written to the memory (see command interface section). see figure 9 , figure 11 and figure 12 read ac waveforms, and ta b l e 2 2 and ta b l e 2 3 read ac characteristics, for details of when the output becomes valid. 3.2 bus write bus write operations write commands to the memory or latch input data to be programmed. a bus write operation is initiated when chip enable and write enable are at v il with output enable at v ih . commands, input data and addresses are latched on the rising edge of write enable or chip enable, whichever occurs first. the addresses can also be latched prior to the write operation by toggling latch enable. in this case the latch enable should be tied to v ih during the bus write operation. see figure 15 and figure 16 , write ac waveforms, and ta b l e 2 4 and ta b l e 2 5 , write ac characteristics, for details of the timing requirements. 3.3 address latch address latch operations input valid addresses. both chip enable and latch enable must be at v il during address latch operations. the addresses are latched on the rising edge of latch enable. 3.4 output disable the outputs are high impedance when the output enable is at v ih . 3.5 standby standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. the memory is in standby when chip enable and reset are at v ih . the power consumption is reduced to the standby level i dd3 and the outputs are set to high impedance, independently from the output enable or write enable inputs. if chip enable switches to v ih during a program or erase operation, the device enters standby mode when finished.
m58lt128gst, m58lt128gsb 3 bus operations 17/98 3.6 reset during reset mode the memory is deselected and the outputs are high impedance. the memory is in reset mode when reset is at v il . the power consumption is reduced to the reset level, independently from the chip enable, output enable or write enable inputs. if reset is pulled to v ss during a program or erase, this operation is aborted and the memory content is no longer valid. table 3. bus operations operation (1) 1. x = don't care. e g w l rp wait (2) 2. wait signal polarity is configured using the set configuration register command. dq15-dq0 bus read v il v il v ih v ih v ih data output bus write v il v ih v il v ih v ih data input address latch v il v ih x v il v ih address input output disable v il v ih v ih v ih v ih hi-z standby v ih xxx v ih hi-z hi-z reset x x x x v il hi-z hi-z
4 command interface m58lt128gst, m58lt128gsb 18/98 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. an internal program/erase controller handles all timings and verifies the correct execution of the program and erase commands. the program/erase controller provides a status register whose output may be read at any time to monitor the progress or the result of the operation. the command interface is reset to read mode when power is first applied, when exiting from reset or whenever v dd is lower than v lko . command sequences must be followed exactly. any invalid combination of commands will be ignored. refer to table 4: command codes , table 5: standard commands , table 6: factory program command , and appendix d: command interface state tables , for a summary of the command interface. note: the security features are described in a dedicated application note. please contact stmicroelectronics for further details. table 4. command codes hex code command 03h set configuration register confirm 10h alternative program setup 20h block erase setup 40h program setup 50h clear status register 70h read status register 80h buffer enhanced factory program 90h read electronic signature 98h read cfi query b0h program/erase suspend c0h program register program d0h program/erase resume, block erase confirm, or buffer program confirm e8h buffer program ffh read array
m58lt128gst, m58lt128gsb 4 command interface 19/98 4.1 read array command the read array command returns the addressed bank to read array mode. one bus write cycle is required to issue the read array command. once a bank is in read array mode, subsequent read operations will output the data from the memory array. a read array command can be issued to any banks while programming or erasing in another bank. if the read array command is issued to a bank currently executing a program or erase operation, the bank will return to read array mode but the program or erase operation will continue, however the data output from the bank is not guaranteed until the program or erase operation has finished. the read modes of other banks are not affected. 4.2 read status register command the device contains a status register that is used to monitor program or erase operations. the read status register command is used to read the contents of the status register for the addressed bank. one bus write cycle is required to issue the read status register command. once a bank is in read status register mode, subsequent read operations will output the contents of the status register. the status register data is latched on the falling edge of the chip enable or output enable signals. either chip enable or output enable must be toggled to update the status register data the read status register command can be issued at any time, even during program or erase operations. the read status register command will only change the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read the status register. a read array command is required to return the bank to read array mode. see ta bl e 9 for the description of the status register bits. 4.3 read electronic signature command the read electronic signature command is used to read the manufacturer and device codes, the protection status of the addressed bank, the configuration register and the protection register. one bus write cycle is required to issue the read electronic signature command. once a bank is in read electronic signature mode, subsequent read operations in the same bank will output the manufacturer code, the device code, the protection status of the addressed bank, or the configuration register (see ta b l e 7 ). the read electronic signature command can be issued at any time, even during program or erase operations, except during protection register program operations. dual operations between the parameter bank and the electronic signature location are not allowed (see table 15: dual operation limitations for details). if a read electronic signature command is issued to a bank that is executing a program or erase operation the bank will go into read electronic signature mode. subsequent bus read
4 command interface m58lt128gst, m58lt128gsb 20/98 cycles will output the electronic signature data and the program/erase controller will continue to program or erase in the background. the read electronic signature command will only change the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read the electronic signature. a read array command is required to return the bank to read array mode. 4.4 read cfi query command the read cfi query command is used to read data from the common flash interface (cfi). one bus write cycle is required to issue the read cfi query command. once a bank is in read cfi query mode, subsequent bus read operations in the same bank read from the common flash interface. the read cfi query command can be issued at any time, even during program or erase operations. if a read cfi query command is issued to a bank that is executing a program or erase operation the bank will go into read cfi query mode. subsequent bus read cycles will output the cfi data and the program/erase controller will continue to program or erase in the background. the read cfi query command will only change the read mode of the addressed bank. the read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read from the cfi. a read array command is required to return the bank to read array mode. dual operations between the parameter bank and the cfi memory space are not allowed (see table 15: dual operation limitations for details). see appendix b: common flash interface , ta bl e 3 6 , ta b l e 3 7 , ta b l e 3 8 , ta bl e 3 9 , ta bl e 4 0 , ta b l e 4 2 , ta b l e 4 3 , ta bl e 4 4 and ta b l e 4 5 for details on the information contained in the common flash interface memory area. 4.5 clear status register command the clear status register command can be used to reset (set to ?0?) all error bits (sr1, 3, 4 and 5) in the status register. one bus write cycle is required to issue the clear status register command. the clear status register command does not affect the read mode of the bank. the error bits in the status register do not automatically return to ?0? when a new command is issued. the error bits in the status register should be cleared before attempting a new program or erase command.
m58lt128gst, m58lt128gsb 4 command interface 21/98 4.6 block erase command the block erase command is used to erase a block. it sets all the bits within the selected block to ?1?. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. two bus write cycles are required to issue the command. 1. the first bus cycle sets up the block erase command. 2. the second latches the block address and starts the program/erase controller. if the second bus cycle is not the block erase confirm code, status register bits sr4 and sr5 are set and the command is aborted. once the command is issued the bank enters read status register mode and any read operation within the addressed bank will output the contents of the status register. a read array command is required to return the bank to read array mode. during block erase operations the bank containing the block being erased will only accept the read array, read status register, read electronic signature, read cfi query and the program/erase suspend command, all other commands will be ignored. the block erase operation aborts if reset, rp , goes to v il . as data integrity cannot be guaranteed when the block erase operation is aborted, the block must be erased again. refer to dual operations section for detailed information about simultaneous operations allowed in banks not being erased. typical erase times are given in table 16: program/erase times and endurance cycles . see appendix c , figure 22: block erase flowchart and pseudo code , for a suggested flowchart for using the block erase command. 4.7 program command the program command is used to program a single word to the memory array. two bus write cycles are required to issue the program command. 1. the first bus cycle sets up the program command. 2. the second latches the address and data to be programmed and starts the program/ erase controller. once the programming has started, read operations in the bank being programmed output the status register content. during a program operation, the bank containing the word being programmed will only accept the read array, read status register, read electronic signature, read cfi query and the program/erase suspend command, all other commands will be ignored. a read array command is required to return the bank to read array mode. refer to dual operations section for detailed information about simultaneous operations allowed in banks not being programmed. typical program times are given in table 16: program/erase times and endurance cycles . the program operation aborts if reset, rp , goes to v il . as data integrity cannot be guaranteed when the program operation is aborted, the word must be reprogrammed.
4 command interface m58lt128gst, m58lt128gsb 22/98 see appendix c , figure 19: program flowchart and pseudo code , for the flowchart for using the program command. 4.8 buffer program command the buffer program command makes use of the device?s 32-word write buffer to speed up programming. up to 32 words can be loaded into the write buffer. the buffer program command dramatically reduces in-system programming time compared to the standard non- buffered program command. four successive steps are required to issue the buffer program command. 1. the first bus write cycle sets up the buffer program command. the setup code can be addressed to any location within the targeted block. after the first bus write cycle, read operations in the bank will output the contents of the status register. status register bit sr7 should be read to check that the buffer is available (sr7 = 1). if the buffer is not available (sr7 = 0), re-issue the buffer program command to update the status register contents. 2. the second bus write cycle sets up the number of words to be programmed. value n is written to the same block address, where n+1 is the number of words to be programmed. 3. use n+1 bus write cycles to load the address and data for each word into the write buffer. addresses must lie within the range from the start address to the start address + n. optimum performance is obtained when the start address corresponds to a 32 word boundary. if the start address is not aligned to a 32 word boundary, the total programming time is doubled 4. the final bus write cycle confirms the buffer program command and starts the program operation. all the addresses used in the buffer program operation must lie within the same block. invalid address combinations or failing to follow the correct sequence of bus write cycles will set an error in the status register and abort the operation without affecting the data in the memory array. if the status register bits sr4 and sr5 are set to '1', the buffer program command is not accepted. clear the status register before re-issuing the command. if the block being programmed is protected an error will be set in the status register and the operation will abort without affecting the data in the memory array. during buffer program operations the bank being programmed will only accept the read array, read status register, read electronic signature, read cfi query and the program/erase suspend command, all other commands will be ignored. refer to dual operations section for detailed information about simultaneous operations allowed in banks not being programmed. see appendix c , figure 20: buffer program flowchart and pseudo code , for a suggested flowchart on using the buffer program command.
m58lt128gst, m58lt128gsb 4 command interface 23/98 4.9 buffer enhanced factory program command the buffer enhanced factory program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. it is used to program one or more write buffer(s) of 32 words to a block. once the device enters buffer enhanced factory program mode, the write buffer can be reloaded any number of times as long as the address remains within the same block. only one block can be programmed at a time. the use of the buffer enhanced factory program command requires certain operating conditions: the targeted block must be unprotected. if it is protected, the user must return the device to read mode. v pp must be set to v pph . v dd must be within operating range. ambient temperature t a must be 30c 10c. the start address must be aligned with the start of a 32 word buffer boundary. the address must remain the start address throughout programming. dual operations are not supported during the buffer enhanced factory program operation and the command cannot be suspended. the buffer enhanced factory program command consists of three phases: the setup phase, the program and verify phase, and the exit phase, see appendix c , figure 25: buffer enhanced factory program flowchart and pseudo code , for a suggested flowchart on using the buffer program command and to table 6: factory program command for details on the buffer enhanced factory program command. 4.9.1 setup phase the buffer enhanced factory program command requires two bus write cycles to initiate the command. 1. the first bus write cycle sets up the buffer enhanced factory program command. 2. the second bus write cycle confirms the command. after the confirm command is issued, read operations output the contents of the status register. the read status register command must not be issued as it will be interpreted as data to program. the status register p/e.c. bit sr7 should be read to check that the p/e.c. is ready to proceed to the next phase. if an error is detected, sr4 goes high (set to ?1?) and the buffer enhanced factory program operation is terminated. see status register section for details on the error.
4 command interface m58lt128gst, m58lt128gsb 24/98 4.9.2 program and verify phase the program and verify phase requires 32 cycles to program the 32 words to the write buffer. the data is stored sequentially, starting at the first address of the write buffer, until the write buffer is full (32 words). to program less than 32 words, the remaining words should be programmed with ffffh. three successive steps are required to issue and execute the program and verify phase of the command. 1. use one bus write operation to latch the start address and the first word to be programmed. the status register bank write status bit sr0 should be read to check that the p/e.c. is ready for the next word. 2. each subsequent word to be programmed is latched with a new bus write operation. the address must remain the start address as the p/e.c. increments the address location.if any address that is not in the same block as the start address is given, the program and verify phase terminates. status register bit sr0 should be read between each bus write cycle to check that the p/e.c. is ready for the next word. 3. once the write buffer is full, the data is programmed sequentially to the memory array. after the program operation the device automatically verifies the data and reprograms if necessary. the program and verify phase can be repeated, without re-issuing the command, to program additional 32 word locations as long as the address remains in the same block. 4. finally, after all words, or the entire block have been programmed, write one bus write operation to any address outside the block containing the start address, to terminate program and verify phase. status register bit sr0 must be checked to determine whether the program operation is finished. the status register may be checked for errors at any time but it must be checked after the entire block has been programmed. 4.9.3 exit phase status register p/e.c. bit sr7 set to ?1? indicates that the device has exited the buffer enhanced factory program operation and returned to read status register mode. a full status register check should be done to ensure that the block has been successfully programmed. see the section on the status register for more details. for optimum performance the buffer enhanced factory program command should be limited to a maximum of 100 program/erase cycles per block. if this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. typical program times are given in ta bl e 1 6 see appendix c , figure 25: buffer enhanced factory program flowchart and pseudo code , for a suggested flowchart on using the buffer enhanced factory program command.
m58lt128gst, m58lt128gsb 4 command interface 25/98 4.10 program/erase suspend command the program/erase suspend command is used to pause a program or block erase operation. the command can be addressed to any bank. the program/erase resume command is required to restart the suspended operation. one bus write cycle is required to issue the program/erase suspend command. once the program/erase controller has paused bits sr7, sr6 and/ or sr2 of the status register will be set to ?1?. the following commands are accepted during program/erase suspend: program/erase resume read array (data from erase-suspended block or program-suspended word is not valid) read status register read electronic signature read cfi query. in addition, if the suspended operation was a block erase then the following commands are also accepted: clear status register program (except in erase-suspended block) buffer program (except in erase suspended blocks) it is possible to accumulate multiple suspend operations. for example: suspend an erase operation, start a program operation, suspend the program operation, then read the array. if a program command is issued during a block erase suspend, the erase operation cannot be resumed until the program operation has completed. the program/erase suspend command does not change the read mode of the banks. if the suspended bank was in read status register, read electronic signature or read cfi query mode the bank remains in that mode and outputs the corresponding data. refer to dual operations section for detailed information about simultaneous operations allowed during program/erase suspend. during a program/erase suspend, the device can be placed in standby mode by taking chip enable to v ih . program/erase is aborted if reset, rp , goes to v il . see appendix c , figure 21: program suspend & resume flowchart and pseudo code , and figure 23: erase suspend & resume flowchart and pseudo code , for flowcharts for using the program/erase suspend command. 4.11 program/erase resume command the program/erase resume command is used to restart the program or erase operation suspended by the program/erase suspend command. one bus write cycle is required to issue the command. the command can be issued to any address. the program/erase resume command does not change the read mode of the banks. if the suspended bank was in read status register, read electronic signature or read cfi query mode the bank remains in that mode and outputs the corresponding data.
4 command interface m58lt128gst, m58lt128gsb 26/98 if a program command is issued during a block erase suspend, then the erase cannot be resumed until the program operation has completed. see appendix c , figure 21: program suspend & resume flowchart and pseudo code , and figure 23: erase suspend & resume flowchart and pseudo code , for flowcharts for using the program/erase resume command. 4.11.1 protection register program command the protection register program command is used to program the user one-time- programmable (otp) segments of the protection register and the two protection register locks. the device features 16 otp segments of 128 bits and one otp segment of 64 bits, as shown in figure 4: protection register map . the segments are programmed one word at a time. when shipped all bits in the segment are set to ?1?. the user can only program the bits to ?0?. two bus write cycles are required to issue the protection register program command. 1. the first bus cycle sets up the protection 2. register program command. 3. the second latches the address and data to be programmed to the protection register and starts the program/erase controller. read operations to the bank being programmed output the status register content after the program operation has started. attempting to program a previously protected protection register will result in a status register error. the protection register program cannot be suspended. dual operations between the parameter bank and the protection register memory space are not allowed (see ta b l e 1 5 : dual operation limitations for details). the two protection register locks are used to protect the otp segments from further modification. the protection of the otp segments is not reversible. refer to figure 4: protection register map , and table 8: protection register lock bits , for details on the lock bits. see appendix c , figure 24: protection register program flowchart and pseudo code , for a flowchart for using the protection register program command. 4.12 set configuration register command the set configuration register command is used to write a new value to the configuration register. two bus write cycles are required to issue the set configuration register command. 1. the first cycle sets up the set configuration register command and the address corresponding to the configuration register content. 2. the second cycle writes the configuration register data and the confirm command. the configuration register data must be written as an address during the bus write cycles, that is dq0 = cr0, dq1 = cr1, ?, dq15 = cr15. addresses a0-a22 are ignored. read operations output the array content after the set configuration register command is issued.
m58lt128gst, m58lt128gsb 4 command interface 27/98 the read electronic signature command is required to read the updated contents of the configuration register. table 5. standard commands commands cycles bus operations (1) 1. x = don't care, wa=word address in targeted bank, rd= read data, srd=status register data, esd=electronic signature data, qd=query data, ba=block address, bka= bank address, pd=program data, pra = protection register address, prd = protection register data, crd=configuration register data. 1st cycle 2nd cycle op. add data op. add data read array 1+ write bka ffh read wa rd read status register 1+ write x 70h read bka (2) 2. must be same bank as in the first cycle. the signature addresses are listed in table 7 srd read electronic signature 1+ write x 90h read bka (2) esd read cfi query 1+ write bka 98h read bka (2) qd clear status register 1 write bka 50h block erase 2 write bka or ba (3) 3. any address within the bank can be used. 20h write ba d0h program 2 write bka or wa (3) 40h or 10h write wa pd buffer program n+4 write ba e8h write ba n write pa 1 pd 1 write pa 2 pd 2 write pa n+1 (4) 4. n+1 is the number of words to be programmed. pd n+1 (4) write x d0h program/erase suspend 1 write x b0h protection register program 2 write pra c0h write pra prd program/erase resume 1 write x d0h set configuration register 2 write crd 60h write crd 03h
4 command interface m58lt128gst, m58lt128gsb 28/98 table 6. factory program command table 7. electronic signature codes command phase cycles bus write operations (1) 1. wa=word address in targeted bank, bka= bank address, pd=program data, ba=block address, x = don?t care. 1st 2nd 3rd final -1 final add data add data add data add data add data buffer enhanced factory program setup 2 bka or wa (2) 2. any address within the bank can be used. 80h wa 1 d0h program/ verify (3) 3. the program/verify phase can be executed any number of times as long as the data is to be programmed to the same block. 32 wa 1 pd 1 wa 1 pd 2 wa 1 pd 3 wa 1 pd 31 wa 1 pd 32 exit 1 not ba 1 (4) 4. wa 1 is the start address, not ba 1 = not block address of wa 1 . x code address (h) data (h) manufacturer code bank address + 00 0020 device code top bank address + 01 88c6h (m58lt128gst) bottom bank address + 01 88c7h (m58lt128gsb) die revision code block address + 03 drc (1) 1. cr = configuration register, drc = die revision code. configuration register bank address + 05 cr (1) protection register pr0 st factory default bank address + 80 bit 0 = ?0? otp area permanently locked bit 1 = ?0? protection register pr0 bank address + 81 bank address + 84 unique device number bank address + 85 bank address + 88 otp area protection register pr1 through pr16 lock bank address + 89 prld protection registers pr1-pr16 bank address + 8a bank address + 109 otp area
m58lt128gst, m58lt128gsb 4 command interface 29/98 figure 4. protection register map ai07563 user programmable otp unique device number protection register lock 1 0 88h 88h 85h 84h 81h 80h user programmable otp protection registers user programmable otp protection register lock 10 432 975 13 12 10 11 8 6 14 15 pr1 pr16 pr0 89h 8ah 91h 102h 109h
4 command interface m58lt128gst, m58lt128gsb 30/98 table 8. protection register lock bits lock description number address bits protection register lock 1 80h bit 0 read-only bit preprogrammed to ?0? protect unique device number (address 81h to 84h in pr0) bit 1 protects 64bits of otp segment (address 85h to 88h in pr0) when set to ?0? default value is ?1? protection register lock 2 89h bit 0 protects 128bits of otp segment pr1 bit 1 protects 128bits of otp segment pr2 bit 2 protects 128bits of otp segment pr3 - - - - - - bit 13 protects 128bits of otp segment pr14 bit 14 protects 128bits of otp segment pr15 bit 15 protects 128bits of otp segment pr16
m58lt128gst, m58lt128gsb 5 status register 31/98 5 status register the status register provides information on the current or previous program or erase operations. issue a read status register command to read the contents of the status register, refer to read status register command section for more details. to output the contents, the status register is latched and updated on the falling edge of the chip enable or output enable signals and can be read until chip enable or output enable returns to v ih . the status register can only be read using single asynchronous or single synchronous reads. bus read operations from any address within the bank, always read the status register during program and erase operations. the various bits convey information about the status and any errors of the operation. bits sr7, sr6, sr2 and sr0 give information on the status of the device and are set and reset by the device. bits sr5, sr4, sr3 and sr1 give information on errors, they are set by the device but must be reset by issuing a clear status register command or a hardware reset. if an error bit is set to ?1? the status register should be reset before issuing another command. refer to table 9: status register bits in conjunction with the following text descriptions. 5.1 program/erase controller status bit (sr7) the program/erase controller status bit indicates whether the program/erase controller is active or inactive in any bank. when the program/erase controller status bit is low (set to ?0?), the program/erase controller is active; when the bit is high (set to ?1?), the program/erase controller is inactive, and the device is ready to process a new command. the program/erase controller status bit is low immediately after a program/erase suspend command is issued until the program/erase controller pauses. after the program/erase controller pauses the bit is high. 5.2 erase suspend status bit (sr6) the erase suspend status bit indicates that an erase operation has been suspended in the addressed block. when the erase suspend status bit is high (set to ?1?), a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. the erase suspend status bit should only be considered valid when the program/erase controller status bit is high (program/erase controller inactive). sr6 is set within the erase suspend latency time of the program/erase suspend command being issued therefore the memory may still complete the operation rather than entering the suspend mode. when a program/erase resume command is issued the erase suspend status bit returns low.
5 status register m58lt128gst, m58lt128gsb 32/98 5.3 erase status bit (sr5) the erase status bit is used to identify if there was an error during a block or bank erase operation. when the erase status bit is high (set to ?1?), the program/erase controller has applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly. the erase status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). once set high, the erase status bit must be set low by a clear status register command or a hardware reset before a new erase command is issued, otherwise the new command will appear to fail. 5.4 program status bit (sr4) the program status bit is used to identify if there was an error during a program operation. the program status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). when the program status bit is high (set to ?1?), the program/erase controller has applied the maximum number of pulses to the word and still failed to verify that it has programmed correctly. attempting to program a '1' to an already programmed bit while v pp = v pph will also set the program status bit high. if v pp is different from v pph , sr4 remains low (set to '0') and the attempt is not shown. once set high, the program status bit must be set low by a clear status register command or a hardware reset before a new program command is issued, otherwise the new command will appear to fail. 5.5 v pp status bit (sr3) the v pp status bit is used to identify an invalid voltage on the v pp pin during program and erase operations. the v pp pin is only sampled at the beginning of a program or erase operation. program and erase operations are not guaranteed if v pp becomes invalid during an operation. when the v pp status bit is low (set to ?0?), the voltage on the v pp pin was sampled at a valid voltage. when the v pp status bit is high (set to ?1?), the v pp pin has a voltage that is below the v pp lockout voltage, v pplk , the memory is protected and program and erase operations cannot be performed. once set high, the v pp status bit must be set low by a clear status register command or a hardware reset before a new program or erase command is issued, otherwise the new command will appear to fail.
m58lt128gst, m58lt128gsb 5 status register 33/98 5.6 program suspend status bit (sr2) the program suspend status bit indicates that a program operation has been suspended in the addressed block. the program suspend status bit should only be considered valid when the program/erase controller status bit is high (program/erase controller inactive). when the program suspend status bit is high (set to ?1?), a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. sr2 is set within the program suspend latency time of the program/erase suspend command being issued therefore the memory may still complete the operation rather than entering the suspend mode. when a program/erase resume command is issued the program suspend status bit returns low. sr1. reserved. 5.7 bank write/multiple word program status bit (sr0) the bank write status bit indicates whether the addressed bank is programming or erasing. in buffer enhanced factory program mode the multiple word program bit shows if the device is ready to accept a new word to be programmed to the memory array. the bank write status bit should only be considered valid when the program/erase controller status sr7 is low (set to ?0?). when both the program/erase controller status bit and the bank write status bit are low (set to ?0?), the addressed bank is executing a program or erase operation. when the program/erase controller status bit is low (set to ?0?) and the bank write status bit is high (set to ?1?), a program or erase operation is being executed in a bank other than the one being addressed. in buffer enhanced factory program mode if multiple word program status bit is low (set to ?0?), the device is ready for the next word, if the multiple word program status bit is high (set to ?1?) the device is not ready for the next word. for further details on how to use the status register, see the flowcharts and pseudo codes provided in appendix c .
5 status register m58lt128gst, m58lt128gsb 34/98 table 9. status register bits 1. logic level '1' is high, '0' is low. bit name type logic level definition sr7 p/e.c. status status '1' ready '0' busy sr6 erase suspend status status '1' erase suspended '0' erase in progress or completed sr5 erase status error '1' erase error '0' erase success sr4 program status error '1' program error '0' program success sr3 v pp status error '1' v pp invalid, abort '0' v pp ok sr2 program suspend status status '1' program suspended '0' program in progress or completed sr1 reserved sr0 bank write status status '1' sr7 = ?1? not allowed sr7 = ?0? program or erase operation in a bank other than the addressed bank '0' sr7 = ?1? no program or erase operation in the device sr7 = ?0? program or erase operation in addressed bank multiple word program status (enhanced factory program mode) status '1' sr7 = ?1? not allowed sr7 = ?0? the device is not ready for the next word '0' sr7 = ?1? the device is exiting from befp sr7 = ?0? the device is ready for the next word
m58lt128gst, m58lt128gsb 6 configuration register 35/98 6 configuration register the configuration register is used to configure the type of bus access that the memory will perform. refer to read modes section for details on read operations. the configuration register is set through the command interface using the set configuration register command. after a reset or power-up the device is configured for asynchronous read (cr15 = 1). the configuration register bits are described in ta bl e 1 0 they specify the selection of the burst length, burst type, burst x latency and the read operation. refer to figure 5 and figure 6 for examples of synchronous burst configurations. 6.1 read select bit (cr15) the read select bit, cr15, is used to switch between asynchronous and synchronous read operations. when the read select bit is set to ?1?, read operations are asynchronous; when the read select bit is set to ?0?, read operations are synchronous. synchronous burst read is supported in both parameter and main blocks and can be performed across banks. on reset or power-up the read select bit is set to ?1? for asynchronous access. 6.2 x-latency bits (cr13-cr11) the x-latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. for correct operation the x-latency bits can only assume the values in table 10: configuration register . the correspondence between x-latency settings and the maximum sustainable frequency must be calculated taking into account some system parameters. two conditions must be satisfied: 1. depending on whether t avk_cpu or t delay is supplied either one of the following two equations must be satisfied: (n + 1) t k t avqv - t avk_cpu + t qvk_cpu (n + 2) t k t avqv + t delay + t qvk_cpu 2. and also t k > t kqv + t qvk_cpu where n is the chosen x-latency configuration code t k is the clock period t avk_cpu is clock to address valid, l low, or e low, whichever occurs last t delay is address valid, l low, or e low to clock, whichever occurs last t qvk_cpu is the data setup time required by the system cpu, t kqv is the clock to data valid time t avqv is the random access time of the device.
6 configuration register m58lt128gst, m58lt128gsb 36/98 refer to figure 5: x-latency and data output configuration example . 6.3 wait polarity bit (cr10) the wait polarity bit is used to set the polarity of the wait signal used in synchronous burst read mode. during synchronous burst read mode the wait signal indicates whether the data output are valid or a wait state must be inserted. when the wait polarity bit is set to ?0? the wait signal is active low. when the wait polarity bit is set to ?1? the wait signal is active high. 6.4 data output configuration bit (cr9) the data output configuration bit is used to configure the output to remain valid for either one or two clock cycles during synchronous mode. when the data output configuration bit is ?0? the output data is valid for one clock cycle, when the data output configuration bit is ?1? the output data is valid for two clock cycles. the data output configuration must be configured using the following condition: t k > t kqv + t qvk_cpu where t k is the clock period t qvk_cpu is the data setup time required by the system cpu t kqv is the clock to data valid time. if this condition is not satisfied, the data output configuration bit should be set to ?1? (two clock cycles). refer to figure 5: x-latency and data output configuration example . 6.5 wait configuration bit (cr8) the wait configuration bit is used to control the timing of the wait output pin, wait, in synchronous burst read mode. when wait is asserted, data is not valid and when wait is deasserted, data is valid. when the wait configuration bit is low (set to ?0?) the wait output pin is asserted during the wait state. when the wait configuration bit is high (set to ?1?), the wait output pin is asserted one data cycle before the wait state. 6.6 burst type bit (cr7) the burst type bit determines the sequence of addresses read during synchronous burst reads. the burst type bit is high (set to ?1?), as the memory outputs from sequential addresses only. see ta bl e 1 1 : b u r s t ty p e d e f i n i t i o n , for the sequence of addresses output from a given starting address in sequential mode.
m58lt128gst, m58lt128gsb 6 configuration register 37/98 6.7 valid clock edge bit (cr6) the valid clock edge bit, cr6, is used to configure the active edge of the clock, k, during synchronous read operations. when the valid clock edge bit is low (set to ?0?) the falling edge of the clock is the active edge. when the valid clock edge bit is high (set to ?1?) the rising edge of the clock is the active edge. 6.8 wrap burst bit (cr3) the wrap burst bit, cr3, is used to select between wrap and no wrap. synchronous burst reads can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). when the wrap burst bit is low (set to ?0?) the burst read wraps. when it is high (set to ?1?) the burst read does not wrap. 6.9 burst length bits (cr2-cr0) the burst length bits are used to set the number of words to be output during a synchronous burst read operation as result of a single address latch cycle. they can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. in continuous burst mode the burst sequence can cross bank boundaries. in continuous burst mode, in 4, 8 or 16 words no-wrap, depending on the starting address, the device asserts the wait signal to indicate that a delay is necessary before the data is output. if the starting address is aligned to an 8 word boundary no wait states are needed and the wait output is not asserted. if the starting address is not aligned to the 8 word boundary, wait will be asserted when the burst sequence crosses the first 16 word boundary to indicate that the device needs an internal delay to read the successive words in the array. in the worst case, the number of wait states is one clock cycle less than the latency setting. the exact number is reported in table 12: wait at the boundary . wait will be asserted only once during a continuous burst access. see also table 11: burst type definition . cr14, cr5 and cr4 are reserved for future use.
6 configuration register m58lt128gst, m58lt128gsb 38/98 table 10. configuration register bit description value description cr15 read select 0 synchronous read 1 asynchronous read (default at power-on) cr14 reserved cr13-cr11 x-latency 010 2 clock latency (1) 1. the combination x-latency=2, data held for two clock cycles and wait active one data cycle before the wait state is not supported. 011 3 clock latency 100 4 clock latency 101 5 clock latency 110 6 clock latency 111 7 clock latency (default) other configurations reserved cr10 wait polarity 0 wait is active low (default) 1 wait is active high cr9 data output configuration 0 data held for one clock cycle 1 data held for two clock cycles (default) (1) cr8 wait configuration 0 wait is active during wait state (default) 1 wait is active one data cycle before wait state (1) cr7 burst type 0 reserved 1 sequential (default) cr6 valid clock edge 0 falling clock edge 1 rising clock edge (default) cr5-cr4 reserved cr3 wrap burst 0wrap 1 no wrap (default) cr2-cr0 burst length 001 4 words 010 8 words 011 16 words 111 continuous (default)
m58lt128gst, m58lt128gsb 6 configuration register 39/98 table 11. burst type definition mode start add. sequential continuous burst 4 words 8 words 16 words wrap 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14- 15 0-1-2-3-4-5-6... 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14- 15-0 1-2-3-4-5-6-7... 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15- 0-1 2-3-4-5-6-7-8... 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0- 1-2 3-4-5-6-7-8-9... ... 7 7-4-5-6 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4- 5-6 7-8-9-10-11-12-13... ... 12 12-13-14-15 12-13-14-15-8-9-10- 11 12-13-14-15-0-1-2-3-4-5-6-7-8-9-10- 11 12-13-14-15-16-17... 13 13-14-15-12 13-14-15-8-9-10-11- 12 13-14-15-0-1-2-3-4-5-6-7-8-9-10-11- 12 13-14-15-16-17-18... 14 14-15-12-13 14-15-8-9-10-11-12- 13 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12- 13 14-15-16-17-18-19... 15 15-12-13-14 15-8-9-10-11-12-13- 14 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13- 14 15-16-17-18-19-20... no-wrap 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14- 15 same as for wrap (wrap /no wrap has no effect on continuous burst) 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8--9-10-11-12-13-14- 15-16 2 2-3-4-5 2-3-4-5-6-7-8-9... 2-3-4-5--6-7-8-9-10-11-12-13-14-15- 16-17 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7-8-9-10-11-12-13-14-15- 16-17-18 ... 7 7-8-9-10 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13-14-15-16-17-18- 19-20-21-22 ... 12 12-13-14-15 12-13-14-15-16-17- 18-19 12-13-14-15-16-17-18-19-20-21-22- 23-24-25-26-27 13 13-14-15-16 13-14-15-16-17-18- 19-20 13-14-15-16-17-18-19-20-21-22-23- 24-25-26-27-28 14 14-15-16-17 14-15-16-17-18-19- 20-21 14-15-16-17-18-19-20-21-22-23-24- 25-26-27-28-29 15 15-16-17-18 15-16-17-18-19-20- 21-22 15-16-17-18-19-20-21-22-23-24-25- 26-27-28-29-30
6 configuration register m58lt128gst, m58lt128gsb 40/98 table 12. wait at the boundary figure 5. x-latency and data output configuration example 1. the settings shown are x-latency = 4, data output held for one clock cycle. start address number of wait states x-latency = 7 x-latency = 6 x-latency = 5 x-latency = 4 x-latency = 3 x-latency = 2 0000000 1000000 2100000 3210000 4321000 5432100 6543210 7654321 ai10262 a22-a0 valid address k l dq15-dq0 valid data x-latency valid data tacc tavk_cpu tk tqvk_cpu tqvk_cpu tkqv 1st cycle 2nd cycle 3rd cycle 4th cycle e tdelay valid address
m58lt128gst, m58lt128gsb 6 configuration register 41/98 figure 6. wait configuration example ai10263 a22-a0 valid address k l dq15-dq0 valid address valid data wait cr8 = '0' cr10 = '0' wait cr8 = '1' cr10 = '0' valid data not valid valid data e wait cr8 = '0' cr10 = '1' wait cr8 = '1' cr10 = '1' g
7 read modes m58lt128gst, m58lt128gsb 42/98 7 read modes read operations can be performed in two different ways depending on the settings in the configuration register. if the clock signal is ?don?t care? for the data output, the read operation is asynchronous; if the data output is synchronized with clock, the read operation is synchronous. the read mode and format of the data output are determined by the configuration register. (see configuration register section for details). all banks support both asynchronous and synchronous read operations. 7.1 asynchronous read modes in asynchronous read operations the clock signal is ?don?t care?. the device outputs the data corresponding to the address latched, that is the memory array, status register, common flash interface or electronic signature depending on the command issued. cr15 in the configuration register must be set to ?1? for asynchronous operations. in asynchronous read mode, the wait signal is always deasserted. the device features an automatic standby mode. during asynchronous read operations, after a bus inactivity of 150ns, the device automatically switches to the automatic standby mode. in this condition the power consumption is reduced to the standby value and the outputs are still driven. asynchronous read operations can be performed in two different ways, asynchronous random read and asynchronous page read. 7.1.1 asynchronous random read asynchronous random read operations are controlled by the latch enable, l , signal. a valid bus operation involves setting the desired address on the address inputs, setting chip enable and latch enable low, v il , and keeping write enable high, v ih . the address is latched on the rising edge of latch enable, l , before the value is output on the data bus. once latched, the address inputs can change. set output enable low, v il , to read the data on the data inputs/outputs. see table 22: asynchronous read ac characteristics , and figure 9: asynchronous random access read ac waveforms for details. 7.1.2 asynchronous page read only asynchronous page read takes full advantage of the internal page storage so different timings are applied. in asynchronous page read mode, a page of data is internally read and stored in a page buffer. the page size is 8 words and is addressed by address inputs a0, a1 and a2. the first read operation within the page has the normal access time (t avqv ), subsequent reads within the same page have much shorter access times (t avqv1 ). if the page changes then the normal longer timings apply again. see table 22: asynchronous read ac characteristics , figure 10: asynchronous page read ac waveforms for details.
m58lt128gst, m58lt128gsb 7 read modes 43/98 7.2 synchronous burst read modes in synchronous burst read mode the data is output in bursts synchronized with the clock. it is possible to perform burst reads across bank boundaries. synchronous burst read mode can only be used to read the memory array. for other read operations, such as read status register, read cfi and read electronic signature, single synchronous read or asynchronous random access read must be used. in synchronous burst read mode the flow of the data output depends on parameters that are configured in the configuration register. a burst sequence starts at the first clock edge (rising or falling depending on valid clock edge bit cr6 in the configuration register) after the falling edge of latch enable or chip enable, whichever occurs last. addresses are internally incremented and data is output on each data cycle after a delay which depends on the x latency bits cr13-cr11 of the configuration register. the number of words to be output during a synchronous burst read operation can be configured as 4 words, 8 words, 16 words or continuous (burst length bits cr2-cr0). the data can be configured to remain valid for one or two clock cycles (data output configuration bit cr9). the order of the data output can be modified through the wrap burst bit in the configuration register. the burst sequence is sequential and can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). the wait signal may be asserted to indicate to the system that an output delay will occur. this delay will depend on the starting address of the burst sequence and on the burst configuration. wait is asserted during the x latency, the wait state and at the end of a 4, 8 and 16 word burst. it is only deasserted when output data are valid or when g is at v ih . in continuous burst read mode a wait state will occur when crossing the first 16 word boundary. if the starting address is aligned to the burst length (4, 8 or 16 words) the wrapped configuration has no impact on the output sequence. the wait signal can be configured to be active low or active high by setting cr10 in the configuration register. see table 23: synchronous read ac characteristics , and figure 11: synchronous burst read ac waveforms , for details. 7.2.1 synchronous burst read suspend a synchronous burst read operation can be suspended, freeing the data bus for other higher priority devices. it can be suspended during the initial access latency time (before data is output) in which case the initial latency time can be reduced to zero, or after the device has output data. when the synchronous burst read operation is suspended, internal array sensing continues and any previously latched internal data is retained. a burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. a synchronous burst read operation is suspended when chip enable, e , is low and the current address has been latched (on a latch enable rising edge or on a valid clock edge). the clock signal is then halted at v ih or at v il , and output enable, g , goes high. when output enable, g , becomes low again and the clock signal restarts, the synchronous burst read operation is resumed exactly where it stopped.
7 read modes m58lt128gst, m58lt128gsb 44/98 wait being gated by e , it will remain active and will not revert to high impedance when g goes high. so if two or more devices are connected to the system?s ready signal, to prevent bus contention the wait signal of the m58lt128gst and m58lt128gsb should not be directly connected to the system?s ready signal. wait will revert to high-impedance when output enable, g , or chip enable, e , goes high. see table 23: synchronous read ac characteristics , and figure 13: synchronous burst read suspend ac waveforms , for details. 7.2.2 single synchronous read mode single synchronous read operations are similar to synchronous burst read operations except that the memory outputs the same data to the end of the operation. synchronous single reads are used to read the electronic signature, status register, cfi, configuration register status, or protection register. when the addressed bank is in read cfi, read status register or read electronic signature mode, the wait signal is deasserted when output enable, g , is at v ih or for the one clock cycle during which output data is valid. otherwise, it is asserted. see table 23: synchronous read ac characteristics , and figure 11: synchronous burst read ac waveforms , for details.
m58lt128gst, m58lt128gsb 8 dual operations and multiple bank architecture 45/98 8 dual operations and multiple bank architecture the multiple bank architecture of the m58lt128gst and m58lt128gsb gives greater flexibility for software developers to split the code and data spaces within the memory array. the dual operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. the dual operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). if a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. also if the suspended operation was erase then a program command can be issued to another block, so the device can have one block in erase suspend mode, one programming and other banks in read mode. bus read operations are allowed in another bank between setup and confirm cycles of program or erase operations. by using a combination of these features, read operations are possible at any moment in the m58lt128gst and m58lt128gsb devices. dual operations between the parameter bank and either of the cfi, or the electronic signature memory space are not allowed. ta b l e 1 5 shows which dual operations are allowed or not between the cfi, the electronic signature locations and the memory array. ta b l e 1 3 and ta bl e 1 4 show the dual operations possible in other banks and in the same bank. table 13. dual operations allowed in other banks status of bank commands allowed in another bank read array read status register read cfi query read electronic signature program, buffer program block erase program/ erase suspend program/ erase resume idle yes yes yes yes yes yes yes yes programming yes yes yes yes ? ? yes ? erasing yes yes yes yes ? ? yes ? program suspended yes yes yes yes ? ? ? yes erase suspended yes yes yes yes yes ? ? yes
8 dual operations and multiple bank architecture m58lt128gst, m58lt128gsb 46/98 table 14. dual operations allowed in same bank table 15. dual operation limitations status of bank commands allowed in same bank read array read status register read cfi query read electronic signature program, buffer program block erase program/ erase suspend program/ erase resume idle yes yes yes yes yes yes yes yes programming ? (1) 1. the read array command is accepted but the data output is not guaranteed until the program or erase has completed. yes yes yes ? ? yes ? erasing ? (1) yes yes yes ? ? yes ? program suspended ye s (2) 2. not allowed in the word that is being erased or programmed. ye s ye s ye s ? ? ? ye s erase suspended ye s (2) ye s ye s ye s ye s (2) ?? yes current status commands allowed read cfi / electronic signature read parameter blocks read main blocks located in parameter bank not located in parameter bank programming / erasing parameter blocks no no no yes programming / erasing main blocks located in parameter bank no no no yes not located in parameter bank no yes yes in different bank only
m58lt128gst, m58lt128gsb 9 program and erase times and endurance cycles 47/98 9 program and erase times and endurance cycles the program and erase times and the number of program/ erase cycles per block are shown in ta b l e 1 6 exact erase times may change depending on the memory array condition. the best case is when all the bits in the block are at ?0? (pre-programmed). the worst case is when all the bits in the block are at ?1? (not preprogrammed). usually, the system overhead is negligible with respect to the erase time. in the m58lt128gst and m58lt128gsb the maximum number of program/erase cycles depends on the v pp voltage supply used. table 16. program/erase times and endurance cycles parameter condition (1)(2) min typ typical after 100kw/e cycles max unit v pp = v dd erase parameter block (16 kword) 0.4 1 2.5 s main block (64 kword) preprogrammed 1 3 4 s not preprogrammed 1.2 4 s program (3) single cell word program 30 60 s buffer program 30 60 s single word word program 90 180 s buffer program 90 180 s buffer (32 words) (buffer program) 440 880 s main block (64 kword) 880 ms suspend latency program 20 25 s erase 20 25 s program/erase cycles (per block) main blocks 100,000 cycles parameter blocks 100,000 cycles
9 program and erase times and endurance cycles m58lt128gst, m58lt128gsb 48/98 v pp = v pph erase parameter block (16 kword) 0.4 2.5 s main block (64 kword) 1 4 s program (3) single cell word program 30 60 s single word word program 85 170 s buffer enhanced factory program (4) 10 s buffer (32 words) buffer program 340 680 s buffer enhanced factory program 320 s main block (64 kwords) buffer program 640 ms buffer enhanced factory program 640 ms bank (16 mbits) buffer program 10 s buffer enhanced factory program 10 s program/erase cycles (per block) main blocks 1000 cycles parameter blocks 2500 cycles 1. t a = ?25 to 85c; v dd = 1.7v to 2v; v ddq = 2.7 to 3.6v. 2. values are liable to change with the external system-le vel overhead (command sequence and status register polling execution). 3. excludes the time needed to execute the command sequence. 4. this is an average va lue on the entire device. parameter condition (1)(2) min typ typical after 100kw/e cycles max unit
m58lt128gst, m58lt128gsb 10 maximum rating 49/98 10 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 17. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature ?25 85 c t bias temperature under bias ?25 85 c t stg storage temperature ?65 125 c v io input or output voltage ?0.5 4.2 v v dd supply voltage ?0.2 2.5 v v ddq input/output supply voltage ?0.6 5 v v pp program voltage ?0.2 10 v i o output short circuit current 100 ma t vpph time for v pp at v pph 100 hours
11 dc and ac parameters m58lt128gst, m58lt128gsb 50/98 11 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 18: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 18. operating and ac measurement conditions figure 7. ac measurement i/o waveform parameter m58lt128gst, m58lt128gsb units 110 min max v dd supply voltage 1.7 2.0 v v ddq supply voltage 2.7 3.6 v v pp supply voltage (factory environment) 8.5 9.5 v v pp supply voltage (application environment) ?0.4 v ddq +0.4 v ambient operating temperature ?25 85 c load capacitance (c l ) 30 pf input rise and fall times 5 ns input pulse voltages 0 to v ddq v input and output timing ref. voltages v ddq /2 v ai06161 v ddq 0v v ddq /2
m58lt128gst, m58lt128gsb 11 dc and ac parameters 51/98 figure 8. ac measurement load circuit table 19. capacitance symbol parameter test condition min (1) 1. sampled only, not 100% tested. max (1) unit c in input capacitance v in = 0v 68pf c out output capacitance v out = 0v 812pf ai06162 v ddq c l c l includes jig capacitance 16.7k ? device under test 0.1f v dd 0.1f v ddq 16.7k ?
11 dc and ac parameters m58lt128gst, m58lt128gsb 52/98 table 20. dc characteristics - currents symbol parameter test condition typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 1 a i dd1 supply current asynchronous read (f=5mhz) e = v il , g = v ih 13 15 ma supply current synchronous read (f=52mhz) 4 word 16 18 ma 8 word 18 20 ma 16 word 23 25 ma continuous 25 27 ma i dd2 supply current (reset) rp = v ss 0.2v 25 70 a i dd3 supply current (standby) e = v dd 0.2v 25 70 a i dd4 supply current (automatic standby) e = v il , g = v ih 25 70 a i dd5 (1) 1. sampled only, not 100% tested. supply current (program) v pp = v pph 815ma v pp = v dd 10 20 ma supply current (erase) v pp = v pph 815ma v pp = v dd 10 20 ma i dd6 (1)(2) 2. v dd dual operation current is the sum of read and program or erase currents. supply current (dual operations) program/erase in one bank, asynchronous read in another bank 23 35 ma program/erase in one bank, synchronous read (continuous f=52mhz) in another bank 35 47 ma i dd7 (1) supply current program/ erase suspended (standby) e = v dd 0.2v 25 70 a i pp1 (1) v pp supply current (program) v pp = v pph 25ma v pp = v dd 0.2 5 a v pp supply current (erase) v pp = v pph 25ma v pp = v dd 0.2 5 a i pp2 v pp supply current (read) v pp v dd 0.2 5 a i pp3 (1) v pp supply current (standby) v pp v dd 0.2 5 a
m58lt128gst, m58lt128gsb 11 dc and ac parameters 53/98 table 21. dc characteristics - voltages symbol parameter test condition min typ max unit v il input low voltage 0 0.4 v v ih input high voltage v ddq ?0.4 v ddq + 0.4 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage i oh = ?100a v ddq ?0.1 v v pp1 v pp program voltage-logic program, erase 1.1 1.8 3.3 v v pph v pp program voltage factory program, erase 8.5 9.0 9.5 v v pplk program or erase lockout 0.4 v v lko v dd lock voltage 1v v rph rp pin extended high voltage 3.3 v
11 dc and ac parameters m58lt128gst, m58lt128gsb 54/98 figure 9. asynchronous random access read ac waveforms ai08311 tavav telqx tehqx tglqv tglqx tghqx dq0-dq15 e g telqv tehqz tghqz valid a0-a22 valid valid l tellh tllqv tlllh tavlh tlhax taxqx wait teltv tehtz note. write enable, w, is high, wait is active low. hi-z hi-z tavqv tgltv tghtz
m58lt128gst, m58lt128gsb 11 dc and ac parameters 55/98 figure 10. asynchronous page read ac waveforms ai08334b a2-a22 e g a0-a2 valid add. l dq0-dq15 valid add. valid add. valid address valid address valid data tlhax tavlh tllqv tavqv1 tglqx tlllh tellh wait tavav telqv telqx teltv tglqv (1) note 1. wait is active low. valid address latch outputs enabled valid data standby hi-z tgltv valid data valid data valid data
11 dc and ac parameters m58lt128gst, m58lt128gsb 56/98 table 22. asynchronous read ac characteristics symbol alt parameter m58lt128gst, m58lt128gsb unit 110 read timings t avav t rc address valid to next address valid min 110 ns t avqv t acc address valid to output valid (random) max 110 ns t avqv1 t pag e address valid to output valid (page) max 25 ns t axqx (1) 1. sampled only, not 100% tested. t oh address transition to output transition min 0 ns t eltv chip enable low to wait valid max 16 ns t elqv (2) 2. g may be delayed by up to t elqv - t glqv after the falling edge of e without increasing t elqv . t ce chip enable low to output valid max 110 ns t elqx (1) t lz chip enable low to output transition max 0 ns t ehtz chip enable high to wait hi-z max 17 ns t ehqx (1) t oh chip enable high to output transition min 0 ns t ehqz (1) t hz chip enable high to output hi-z max 17 ns t glqv (2) t oe output enable low to output valid max 30 ns t glqx (1) t olz output enable low to output transition min 0 ns t gltv output enable low to wait valid max 17 ns t ghqx (1) t oh output enable high to output transition min 0 ns t ghqz (1) t df output enable high to output hi-z max 17 ns t ghtz t df output enable high to wait hi-z max 17 ns latch timings t avlh t avadvh address valid to latch enable high min 11 ns t ellh t eladvh chip enable low to latch enable high min 10 ns t lhax t advhax latch enable high to address transition min 9 ns t lllh t advladvh latch enable pulse width min 11 ns t llqv t advlqv latch enable low to output valid (random) max 110 ns
m58lt128gst, m58lt128gsb 11 dc and ac parameters 57/98 figure 11. synchronous burst read ac waveforms ai08309 dq0-dq15 e g a0-a22 l wait k (4) valid valid valid address tlllh tavlh tglqx tavkh tllkh telkh tkhax tkhqx tkhqv not valid valid note 1 note 2 note 2 tkhtx tkhtv tehqx tehqz tghqx tghqz tkhtx hi-z valid note 2 teltv tkhtv tehtz address latch x latency valid data flow boundary crossing valid data standby note 1. the number of clock cycles to be inserted depends on the x latency set in the burst configuration register. 2. the wait signal can be configured to be active during wait state or one cycle before. wait signal is active low. 3. address latched and data output on the rising clock edge. 4. either the rising or the falling edge of the clock signal, k, can be configured as the active edge. here, the activ e edge of k is the rising one. tehel tkhqv tkhqx tkhqv tkhqx hi-z tgltv
11 dc and ac parameters m58lt128gst, m58lt128gsb 58/98 figure 12. single synchronous read ac waveforms ai08312 e g a0-a22 l wait (1,2) k (2) valid address tglqv tavkh tllkh telkh hi-z telqx tkhqv note 1. the wait signal is configured to be active during wait state. wait signal is active low. 2. address latched and data output on the rising clock edge. either the rising or the falling edge of the clock signal , k, can be configured as the active edge. here, the active edge is the rising one. tglqx tkhtv dq0-dq15 valid hi-z telqv tgltv tghtz
m58lt128gst, m58lt128gsb 11 dc and ac parameters 59/98 figure 13. synchronous burst read suspend ac waveforms ai08308 dq0-dq15 e g a0-a22 l wait (2) k (4) valid valid valid address tlllh tavlh tglqv tavkh tllkh telkh tkhax not valid not valid note 1 tehqx tehqz tghqx tghqz hi-z teltv tkhqv tehtz note 1. the number of clock cycles to be inserted depends on the x latency set in the configuration register. 2. the wait signal is configured to be active during wait state. wait signal is active low. 3. the clock signal can be held high or low 4. address latched and data output on the rising clock edge. either the rising or the falling edge of the clock signal , k, can be configured as the active edge. here, the active edge is the rising one. tglqx tehel tghqz tglqv note 3 hi-z tgltv tghtz tgltv
11 dc and ac parameters m58lt128gst, m58lt128gsb 60/98 figure 14. clock input ac waveform table 23. synchronous read ac characteristics symbol alt parameter (1) 1. sampled only, not 100% tested. for other timings please refer to table 22: asynchronous read ac characteristics . m58lt128gst, m58lt128gsb unit 110 synchronous read timings t avkh t avclkh address valid to clock high min 11 ns t elkh t elclkh chip enable low to clock high min 11 ns t eltv chip enable low to wait valid max 16 ns t ehel chip enable pulse width (subsequent synchronous reads) min 17 ns t ehtz chip enable high to wait hi-z max 17 ns t gltv output enable low to wait valid max 17 ns t khax t clkhax clock high to address transition min 10 ns t khqv t khtv t clkhqv clock high to output valid clock high to wait valid max 17 ns t khqx t khtx t clkhqx clock high to output transition clock high to wait transition min 3 ns t llkh t advlclkh latch enable low to clock high min 11 ns t ghtz t df output enable high to wait hi-z max 17 ns clock specifications t khkh t clk clock period (f=52mhz) min 19 ns t khkl t klkh clock high to clock low clock low to clock high min 6 ns t f , t r clock fall or rise time max 2 ns ai06981 tkhkh tf tr tkhkl tklkh
m58lt128gst, m58lt128gsb 11 dc and ac parameters 61/98 figure 15. write ac waveforms, write enable controlled e g w dq0-dq15 command cmd or data status register v pp valid address a0-a22 tavav tqvvpl tavwh twhax program or erase telwl twheh twhdx tdvwh twlwh twhwl tvphwh set-up command confirm command or data input status register read 1st polling telqv ai08016c twhgl twhel bank address valid address l tavlh tlllh tellh tlhax tghwl twhvpl telkv k twhll twhav
11 dc and ac parameters m58lt128gst, m58lt128gsb 62/98 table 24. write ac characteristics, write enable controlled symbol alt parameter (1) 1. sampled only, not 100% tested. m58lt128gst, m58lt128gsb unit 110 write enable controlled timings t avav t wc address valid to next address valid min 110 ns t avlh address valid to latch enable high min 11 ns t avwh (2) 2. these timings are meaningful only if latch enable, l , is always kept low, v il . address valid to write enable high min 50 ns t dvwh t ds data valid to write enable high min 50 ns t ellh chip enable low to latch enable high min 11 ns t elwl t cs chip enable low to write enable low min 0 ns t elqv chip enable low to output valid min 110 ns t elkv chip enable low to clock valid min 9 ns t ghwl output enable high to write enable low min 17 ns t lhax latch enable high to address transition min 9 ns t lllh latch enable pulse width min 11 ns t whav (2) write enable high to address valid min 0 ns t whax (2) write enable high to address transition min 0 ns t whdx t dh write enable high to input transition min 0 ns t wheh t ch write enable high to chip enable high min 0 ns t whel (3) 3. t whel has the values shown when reading in the targeted bank. system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing a command. if it is a read array operation in a different bank t whel is 0ns. write enable high to chip enable low min 25 ns t whll write enable high to latch enable low min 0 ns t whwl t wph write enable high to write enable low min 25 ns t wlwh t wp write enable low to write enable high min 50 ns protection timings t qvvpl output (status register) valid to v pp low min 0 ns t vphwh t vps v pp high to write enable high min 200 ns t whvpl write enable high to v pp low min 200 ns
m58lt128gst, m58lt128gsb 11 dc and ac parameters 63/98 figure 16. write ac waveforms, chip enable controlled w g e dq0-dq15 command cmd or data status register v pp valid address a0-a22 tavav tqvvpl taveh tehax program or erase twlel tehwh tehdx tdveh teleh tehel tvpheh set-up command confirm command or data input status register read 1st polling telqv ai08017c tehgl twhel bank address valid address l tavlh tlllh tlhax tghel tehvpl telkv k tellh
11 dc and ac parameters m58lt128gst, m58lt128gsb 64/98 table 25. write ac characteristics, chip enable controlled symbol alt parameter (1) 1. sampled only, not 100% tested. m58lt128gst, m58lt128gsb unit 110 chip enable controlled timings t avav t wc address valid to next address valid min 110 ns t aveh address valid to chip enable high min 50 ns t avlh address valid to latch enable high min 11 ns t dveh t ds data valid to chip enable high min 50 ns t ehax t ah chip enable high to address transition min 0 ns t ehdx t dh chip enable high to input transition min 0 ns t ehel t wph chip enable high to chip enable low min 25 ns t ehgl chip enable high to output enable low min 0 ns t ehwh t ch chip enable high to write enable high min 0 ns t elkv chip enable low to clock valid min 7 ns t eleh t wp chip enable low to chip enable high min 50 ns t ellh chip enable low to latch enable high min 11 ns t elqv chip enable low to output valid min 110 ns t ghel output enable high to chip enable low min 17 ns t lhax latch enable high to address transition min 9 ns t lllh latch enable pulse width min 11 ns t whel (2) 2. t whel has the values shown when reading in the targeted bank. system designers should take this into account and may insert a software no-op instruction to delay the first read in the same bank after issuing a command. if it is a read array operation in a different bank t whel is 0ns. write enable high to chip enable low min 25 ns t wlel t cs write enable low to chip enable low min 0 ns protection timings t ehvpl chip enable high to v pp low min 200 ns t qvvpl output (status register) valid to v pp low min 0 ns t vpheh t vps v pp high to chip enable high min 200 ns
m58lt128gst, m58lt128gsb 11 dc and ac parameters 65/98 figure 17. reset and power-up ac waveforms table 26. reset and power-up ac characteristics symbol parameter test condition 110 unit t plwl t plel t plgl t plll reset low to write enable low, chip enable low, output enable low, latch enable low during program min 25 s during erase min 25 s other conditions min 110 ns t phwl t phel t phgl t phll reset high to write enable low chip enable low output enable low latch enable low min 30 ns t plph (1)(2) 1. the device reset is possible but not guaranteed if t plph < 50ns. 2. sampled only, not 100% tested. rp pulse width min 50 ns t vdhph (3) 3. it is important to assert rp in order to allow proper cpu initialization during power-up or reset. supply voltages high to reset high min 100 s ai06976 w, rp e, g, vdd, vddq tvdhph tplph power-up reset tplwl tplel tplgl tplll l tphwl tphel tphgl tphll
12 package mechanical m58lt128gst, m58lt128gsb 66/98 12 package mechanical figure 18. tbga64 10x13mm - 8x8 active ball array, 1mm pitch, bottom view package outline 1. drawing is not to scale. table 27. tbga64 10x13mm - 8x8 active ball array, 1mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.300 0.200 0.350 0.0118 0.0079 0.0138 a2 0.800 0.0315 b 0.350 0.500 0.0138 0.0197 d 10.000 9.900 10.100 0.3937 0.3898 0.3976 d1 7.000 ? ? 0.2756 ? ? ddd 0.100 0.0039 e 1.000 ? ? 0.0394 ? ? e 13.000 12.900 13.100 0.5118 0.5079 0.5157 e1 7.000 ? ? 0.2756 ? ? fd 1.500 ? ? 0.0591 ? ? fe 3.000 ? ? 0.1181 ? ? sd 0.500 ? ? 0.0197 ? ? se 0.500 ? ? 0.0197 ? ? e1 e d1 d eb sd se a2 a1 a bga-z23 ddd fd fe ball "a1"
m58lt128gst, m58lt128gsb 13 part numbering 67/98 13 part numbering table 28. ordering information scheme example: m58lt128gs t 1 za 5 e device type m58 architecture l = multilevel, multiple bank, burst mode operating voltage t = v dd = 1.7v to 2.0v, v ddq =2.7v to 3.6v density 128 = 128 mbit (x16) technology g = 0.13m security s = security parameter location t = top boot b = bottom boot speed 1 = 110ns package za = tbga64, 10 x 13mm, 1mm pitch temperature range 5 = ?25 to 85c packing option blank = standard packing e = ecopack package, standard packing f =ecopack package, 24mm tape & reel packing
13 part numbering m58lt128gst, m58lt128gsb 68/98 table 29. daisy chain ordering scheme devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m58lt128gs -za e device type m58lt128gs daisy chain za = tbga64, 10 x 13mm, 1mm pitch option blank = standard packing e = ecopack package, standard packing
m58lt128gst, m58lt128gsb 13 part numbering 69/98 appendix a block address tables the following set of equations can be used to calculate a complete set of block addresses for the m58lt128gst and m58lt128gsb using the information contained in ta bl e 3 0 to ta b l e 3 5 . to calculate the block base address from the block number: first it is necessary to calculate the bank number and the block number offset. this can be achieved using the following formulas: bank_number = (block_number ? 3) / 16 block_number_offset = block_number ? 3 ? (bank_number x 16) if bank_number = 0, the block base address can be directly read from ta b l e 3 0 and ta b l e 3 3 (parameter bank block addresses) in the address range column, in the row that corresponds to the given block number. otherwise: block_base_address = bank_base_address + block_base_address_offset to calculate the bank number and the block number from the block base address: if the address is in the range of the parameter bank, the bank number is 0 and the block number can be directly read from ta b l e 3 0 for the m58lt128gst and ta b l e 3 3 for the m58lt128gsb (parameter bank block addresses), in the block number column, in the row that corresponds to the address given. otherwise, the block number can be calculated using the formulas below: for the top configuration (m58lt128gst): block_number = ((not address) / 2 16 ) + 3 for the bottom configuration (m58lt128gsb): block_number = (address / 2 16 ) + 3 for both configurations the bank number and the block number offset can be calculated using the following formulas: bank_number = (block_number ? 3) / 16 block_number_offset = block_number ? 3 ? (bank_number x 16)
13 part numbering m58lt128gst, m58lt128gsb 70/98 table 30. m58lt128gst - parameter bank block addresses table 31. m58lt128gst - main bank base addresses 1. there are two bank regions: bank re gion 1 contains all the banks that are made up of main blocks only; bank region 2 contains the banks that are made up of the parameter and main blocks (parameter bank). block number size (kwords) address range 0 16 7fc000-7fffff 1 16 7f8000-7fbfff 2 16 7f4000-7f7fff 3 16 7f0000-7f3fff 4 64 7e0000-7effff 5 64 7d0000-7dffff 6 64 7c0000-7cffff 7 64 7b0000-7bffff 8 64 7a0000-7affff 9 64 790000-79ffff 10 64 780000-78ffff bank number block numbers bank base address 1 11-18 700000 2 19-26 680000 3 27-34 600000 4 35-42 580000 5 43-50 500000 6 51-58 480000 7 59-66 400000 8 67-74 380000 9 75-82 300000 10 83-90 280000 11 91-98 200000 12 99-106 180000 13 107-114 100000 14 115-122 080000 15 123-130 000000
m58lt128gst, m58lt128gsb 13 part numbering 71/98 table 32. m58lt128gst - block addresses in main banks table 33. m58lt128gsb - parameter bank block addresses block number offset block base address offset 0 070000 1 060000 2 050000 3 040000 4 030000 5 020000 6 010000 7 000000 block number size (kwords) address range 10 64 070000-07ffff 9 64 060000-06ffff 8 64 050000-05ffff 7 64 040000-04ffff 6 64 030000-03ffff 5 64 020000-02ffff 4 64 010000-01ffff 3 16 00c000-00ffff 2 16 008000-00bfff 1 16 004000-007fff 0 16 000000-003fff
13 part numbering m58lt128gst, m58lt128gsb 72/98 table 34. m58lt128gsb- main bank base addresses 1. there are two bank regions: bank re gion 2 contains all the banks that are made up of main blocks only; bank region 1 contains the banks that are made up of the parameter and main blocks (parameter bank). table 35. m58lt128gsb - block addresses in main banks bank number block numbers bank base address 15 123-130 780000 14 115-122 700000 13 107-114 680000 12 99-106 600000 11 91-98 580000 10 83-90 500000 9 75-82 480000 8 67-74 400000 7 59-66 380000 6 51-58 300000 5 43-50 280000 4 35-42 200000 3 27-34 180000 2 19-26 100000 1 11-18 080000 block number offset block base address offset 7 070000 6 060000 5 050000 4 040000 3 030000 2 020000 1 010000 0 000000
m58lt128gst, m58lt128gsb 13 part numbering 73/98 appendix b common flash interface the common flash interface is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. the system can interface easily with the device, enabling the software to upgrade itself when necessary. when the read cfi query command is issued the device enters cfi query mode and the data structure is read from the memory. ta b l e 3 6 , ta b l e 3 7 , ta b l e 3 8 , ta b l e 3 9 , ta b l e 4 0 , ta b l e 4 2 , ta b l e 4 3 , ta bl e 4 4 and ta b l e 4 5 show the addresses used to retrieve the data. the query data is always presented on the lowest order data outputs (dq0-dq7), the other outputs (dq8-dq15) are set to 0. the cfi data structure also contains a security area where a 64 bit unique security number is written (see figure 4: protection register map ). this area can be accessed only in read mode by the final user. it is impossible to change the security number after it has been written by st. issue a read array command to return to read mode. table 36. query structure overview 1. the flash memory display the cfi data structure when cfi quer y command is issued. in this table are listed the main sub- sections detailed in table 37 , table 38 , table 39 and table 40 . query data is always presented on the lowest order data outputs. offset sub-section name description 000h reserved reserved for algorithm-specific information 010h cfi query identification string command set id and algorithm data offset 01bh system interface information device timing & voltage information 027h device geometry definition flash device layout p primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) 080h security code area lock protection register unique device number and user programmable otp
13 part numbering m58lt128gst, m58lt128gsb 74/98 table 37. cfi query identification string table 38. cfi query system interface information offset sub-section name description value 000h 0020h manufacturer code st 001h 88c6h 88c7h device code m58lt128gst m58lt128gsb to p bottom 002h reserved reserved 003h drc die revision code 004h-00fh reserved reserved 010h 0051h query unique ascii string "qry" "q" 011h 0052h "r" 012h 0059h "y" 013h 0001h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm 014h 0000h 015h offset = p = 000ah address for primary algorithm extended query table (see ta bl e 4 0 ) p = 10ah 016h 0001h 017h 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 018h 0000h 019h value = a = 0000h address for alternate algorithm extended query table na 01ah 0000h offset data description value 01bh 0017h v dd logic supply minimum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 1.7v 01ch 0020h v dd logic supply maximum program/erase or write voltage bit 7 to 4 bcd value in volts bit 3 to 0 bcd value in 100 millivolts 2v 01dh 0085h v pp [programming] supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 8.5v 01eh 0095h v pp [programming] supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 millivolts 9.5v 01fh 0008h typical time-out per single byte/word program = 2 n s 256s 020h 0009h typical time-out for buffer program = 2 n s 512s 021h 000ah typical time-out per individual block erase = 2 n ms 1s 022h 0000h typical time-out for full chip erase = 2 n ms na
m58lt128gst, m58lt128gsb 13 part numbering 75/98 table 39. device geometry definition 023h 0001h maximum time-out for word program = 2 n times typical 512s 024h 0001h maximum time-out for buffer program = 2 n times typical 1024s 025h 0002h maximum time-out per individual block erase = 2 n times typical 4s 026h 0000h maximum time-out for chip erase = 2 n times typical na offset data description value 027h 0018h device size = 2 n in number of bytes 16 mbytes 028h 029h 0001h 0000h flash device interface code description x16 async. 02ah 02bh 0006h 0000h maximum number of bytes in multi-byte program or page = 2 n 64 bytes 02ch 0002h number of identical sized erase block regions within the device bit 7 to 0 = x = number of erase block regions 2 top devices 02dh 02eh 007eh 0000h erase block region 1 information number of identical-size erase blocks = 007eh+1 127 02fh 030h 0000h 0002h erase block region 1 information block size in region 1 = 0200h * 256 byte 128 kbyte 031h 032h 0003h 0000h erase block region 2 information number of identical-size erase blocks = 0003h+1 4 033h 034h 0080h 0000h erase block region 2 information block size in region 2 = 0080h * 256 byte 32 kbyte 035h 038h reserved reserved for future erase block region information na bottom devices 02dh 02eh 0003h 0000h erase block region 1 information number of identical-size erase block = 0003h+1 4 02fh 030h 0080h 0000h erase block region 1 information block size in region 1 = 0080h * 256 bytes 32 kbytes 031h 032h 007eh 0000h erase block region 2 information number of identical-size erase block = 007eh+1 127 033h 034h 0000h 0002h erase block region 2 information block size in region 2 = 0200h * 256 bytes 128 kbytes 035h 038h reserved reserved for future erase block region information na offset data description value
13 part numbering m58lt128gst, m58lt128gsb 76/98 table 40. primary algorithm-specific extended query table offset data description value (p)h = 10ah 0050h primary algorithm extended query table unique ascii string ?pri? "p" 0052h "r" 0049h "i" (p+3)h =10dh 0031h major version number, ascii "1" (p+4)h = 10eh 0033h minor version number, ascii "3" (p+5)h = 10fh 00e6h extended query table contents for primary algorithm. address (p+5)h contains less significant byte. bit 0 chip erase supported(1 = yes, 0 = no) bit 1 erase suspend supported(1 = yes, 0 = no) bit 2 program suspend supported(1 = yes, 0 = no) bit 3 reserved bit 5 instant individual block locking supported(1 = yes, 0 = no) bit 6 protection bits supported(1 = yes, 0 = no) bit 7 page mode read supported(1 = yes, 0 = no) bit 8 synchronous read supported(1 = yes, 0 = no) bit 9 simultaneous operation supported(1 = yes, 0 = no) bit 10 to 31 reserved; undefined bits are ?0?. if bit 31 is ?1? then another 31 bit field of optional features follows at the end of the bit-30 field. no ye s ye s no no ye s ye s ye s ye s ye s 0003h (p+7)h = 111h 0000h (p+8)h = 112h 0000h (p+9)h = 113h 0001h supported functions after suspend read array, read status register and cfi query bit 0 program supported after erase suspend (1 = yes, 0 = no) bit 7 to 1 reserved; undefined bits are ?0? ye s (p+a)h = 114h 0003h reserved (p+b)h = 115h 0000h (p+c)h = 116h 0018h v dd logic supply optimum program/erase voltage (highest performance) bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 1.8v (p+d)h = 117h 0090h v pp supply optimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 9v
m58lt128gst, m58lt128gsb 13 part numbering 77/98 table 41. protection register information table 42. burst read information offset data description value (p+e)h = 118h 0002h number of protection register fields in jedec id space. 0000h indicates that 256 fields are available. 2 (p+f)h = 119h 0080h protection field 1: protection description bits 0-7 lower byte of protection register address bits 8-15 upper byte of protection register address bits 16-23 2 n bytes in factory pre-programmed region bits 24-31 2 n bytes in user programmable region 80h (p+10)h = 11ah 0000h 00h (p+11)h = 11bh 0003h 8 bytes (p+12)h = 11ch 0003h 8 bytes (p+13)h = 11dh 0089h protection register 2: protection description bits 0-31 protection register address bits 32-39 n number of factory programmed regions (lower byte) bits 40-47 n number of factory programmed regions (upper byte) bits 48-55 2 n bytes in factory programmable region bits 56-63 n number of user programmable regions (lower byte) bits 64-71 n number of user programmable regions (upper byte) bits 72-79 2 n bytes in user programmable region 89h (p+14)h = 11eh 0000h 00h (p+15)h = 11fh 0000h 00h (p+16)h = 120h 0000h 00h (p+17)h = 121h 0000h 0 (p+18)h = 122h 0000h 0 (p+19)h = 123h 0000h 0 (p+1a)h = 124h 0010h 16 (p+1b)h = 125h 0000h 0 (p+1c)h = 126h 0004h 16 offset data description value (p+1d)h = 127h 0004h page-mode read capability bits 0-7 n? such that 2 n hex value represents the number of read-page bytes. see offset 0028h for device word width to determine page-mode data output width. 16 bytes (p+1e)h = 128h 0004h number of synchronous mode read configuration fields that follow. 4 (p+1f)h = 129h 0001h synchronous mode read capability configuration 1 bit 3-7 reserved bit 0-2 n? such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device?s burstable address space. this field?s 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. see offset 0028h for word width to determine the burst data output width. 4 (p+20)h = 12ah 0002h synchronous mode read capability configuration 2 8 (p-21)h = 12bh (p+22)h = 12ch 0003h 0007h synchronous mode read capability configuration 3 16 synchronous mode read capability configuration 4 cont.
13 part numbering m58lt128gst, m58lt128gsb 78/98 table 43. bank and erase block region information 1. the variable p is a pointer which is defined at cfi offset 015h. 2. bank regions. there are two bank regions, see table 30 to table 35 . flash memory (top) flash memory (bottom) description offset data offset data (p+23)h = 12dh 02h (p+23)h = 12dh 02h number of bank regions within the device
m58lt128gst, m58lt128gsb 13 part numbering 79/98 table 44. bank and erase block region 1 information flash memory (top) flash memory (bottom) description offset data offset data (p+24)h = 12eh 0fh (p+24)h = 12eh 01h number of identical banks within bank region 1 (p+25)h = 12fh 00h (p+25)h = 12fh 00h (p+26)h = 130h 11h (p+26)h = 130h 11h number of program or erase operations allowed in bank region 1: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+27)h = 131h 00h (p+27)h = 131h 00h number of program or erase operations allowed in other banks while a bank in same region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+28)h = 132h 00h (p+28)h = 132h 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+29)h = 133h 01h (p+29)h = 133h 02h types of erase block regions in bank region 1 n = number of erase block regions with contiguous same-size erase blocks. symmetrically blocked banks have one blocking region (2) . (p+2a)h = 134h 07h (p+2a)h = 134h 03h bank region 1 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+2b)h = 135h 00h (p+2b)h = 135h 00h (p+2c)h = 136h 00h (p+2c)h = 136h 80h (p+2d)h = 137h 02h (p+2d)h = 137h 00h (p+2e)h = 138h 64h (p+2e)h = 138h 64h bank region 1 (erase block type 1) minimum block erase cycles 1000 (p+2f)h = 139h 00h (p+2f)h = 139h 00h (p+30)h = 13ah 02h (p+30)h = 13ah 02h bank region 1 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+31)h = 13bh 03h (p+31)h = 13bh 03h bank region 1 (erase block type 1): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved
13 part numbering m58lt128gst, m58lt128gsb 80/98 1. the variable p is a pointer which is defined at cfi offset 015h. 2. bank regions. there are two bank regions, see table 30 to table 35 . (p+32)h = 13ch 06h bank region 1 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+33)h = 13dh 00h (p+34)h = 13eh 00h (p+35)h = 13fh 02h (p+36)h = 140h 64h bank region 1 (erase block type 2) minimum block erase cycles 1000 (p+37)h = 141h 00h (p+38)h = 142h 02h bank regions 1 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+39)h = 143h 03h bank region 1 (erase block type 2): page mode and synchronous mode capabilities bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved flash memory (top) flash memory (bottom) description offset data offset data
m58lt128gst, m58lt128gsb 13 part numbering 81/98 table 45. bank and erase block region 2 information flash memory (top) flash memory (bottom) description offset data offset data (p+32)h = 13ch 01h (p+3a)h = 144h 0fh number of identical banks within bank region 2 (p+33)h = 13dh 00h (p+3b)h = 145h 00h (p+34)h = 13eh 11h (p+3c)h = 146h 11h number of program or erase operations allowed in bank region 2: bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+35)h = 13fh 00h (p+3d)h = 147h 00h number of program or erase operations allowed in other banks while a bank in this region is programming bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+36)h = 140h 00h (p+3e)h = 148h 00h number of program or erase operations allowed in other banks while a bank in this region is erasing bits 0-3: number of simultaneous program operations bits 4-7: number of simultaneous erase operations (p+37)h = 141h 02h (p+3f)h = 149h 01h types of erase block regions in bank region 2 n = number of erase block regions with contiguous same- size erase blocks. symmetrically blocked banks have one blocking region. (2) (p+38)h = 142h 06h (p+40)h = 14ah 07h bank region 2 erase block type 1 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+39)h = 143h 00h (p+41)h = 14bh 00h (p+3a)h = 144h 00h (p+42)h = 14ch 00h (p+3b)h = 145h 02h (p+43)h = 14dh 02h (p+3c)h = 146h 64h (p+44)h = 14eh 64h bank region 2 (erase block type 1) minimum block erase cycles 1000 (p+3d)h = 147h 00h (p+45)h = 14fh 00h (p+3e)h = 148h 02h (p+46)h = 150h 02h bank region 2 (erase block type 1): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+3f)h = 149h 03h (p+47)h = 151h 03h bank region 2 (erase block type 1):page mode and synchronous mode capabilities (defined in ta bl e 4 2 ) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+40)h = 14ah 03h bank region 2 erase block type 2 information bits 0-15: n+1 = number of identical-sized erase blocks bits 16-31: n256 = number of bytes in erase block region (p+41)h = 14bh 00h (p+42)h = 14ch 80h (p+43)h = 14dh 00h
13 part numbering m58lt128gst, m58lt128gsb 82/98 1. the variable p is a pointer which is defined at cfi offset 015h. 2. bank regions. there ar e two bank regions, see table 30 to table 32 for the m58lt128gst and table 33 to table 35 for the m58lt128gsb. (p+44)h = 14eh 64h bank region 2 (erase block type 2) minimum block erase cycles 1000 (p+45)h = 14fh 00h (p+46)h = 150h 02h bank region 2 (erase block type 2): bits per cell, internal ecc bits 0-3: bits per cell in erase region bit 4: reserved for ?internal ecc used? bits 5-7: reserved (p+47)h = 151h 03h bank region 2 (erase block type 2): page mode and synchronous mode capabilities (defined in ta bl e 4 2 ) bit 0: page-mode reads permitted bit 1: synchronous reads permitted bit 2: synchronous writes permitted bits 3-7: reserved (p+48)h = 152h (p+48)h = 152h feature space definitions (p+49)h = 153h (p+43)h = 153h reserved flash memory (top) flash memory (bottom) description offset data offset data
m58lt128gst, m58lt128gsb 13 part numbering 83/98 appendix c flowcharts and pseudo codes figure 19. program flowchart and pseudo code 1. status check of sr1 (protected block), sr3 (v pp invalid) and sr4 (program error) can be made after each program operation or after a sequence. 2. if an error is found, the status register must be cleared before further program /erase controller operations. 3. any address within the bank can equally be used. write 40h or 10h (3) ai06170b start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0x40); /*writetoflash (addresstoprogram, 0x10);*/ /*see note (3)*/ do { status_register=readflash (addresstoprogram); "see note (3)"; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
13 part numbering m58lt128gst, m58lt128gsb 84/98 figure 20. buffer program flowchart and pseudo code 1. n + 1 is the number of data being programmed. 2. next program data is an element belonging to buffer_progr am[].data; next program address is an element belonging to buffer_program[].address. 3. routine for error check by reading sr3, sr4 and sr1. buffer program e8h command, start address ai08913b start write buffer data, start address yes x = n end no write n (1) , start address x = 0 write next buffer data, next program address x = x + 1 program buffer to flash confirm d0h read status register no sr7 = 1 yes full status register check (3) (2) read status register no sr7 = 1 yes buffer_program_command (start_address, n, buffer_program[] ) /* buffer_program [] is an array structure used to store the address and data to be programmed to the flash memory (the address must be within the segment start address and start address+n) */ { do {writetoflash ( start _address, 0xe8) ; status_register=readflash ( start _address); } while (status_register.sr7==0); writetoflash ( start _address, n); writetoflash (buffer_program[0].address, buffer_program[0].data); /*buffer_program[0].address is the start address*/ x = 0; while (x m58lt128gst, m58lt128gsb 13 part numbering 85/98 figure 21. program suspend & resume flowchart and pseudo code 1. the read status register command (write 70h) can be issued just before or just after the program resume command. write 70h ai10117 read status register yes no sr7 = 1 yes no sr2 = 1 write d0h read data from another address start write b0h program complete write ffh program_suspend_command ( ) { writetoflash (any_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if program has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr2==0) /*program completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_data ( ); /*read data from another address*/ writetoflash (any_address, 0xd0) ; /*write 0xd0 to resume program*/ writetoflash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } } write ffh program continues with bank in read status register mode read status register write 70h (1)
13 part numbering m58lt128gst, m58lt128gsb 86/98 figure 22. block erase flowchart and pseudo code 1. if an error is found, the status register must be cleared before further program/erase operations. 2. any address within the bank can equally be used. write 20h (2) ai06174b start write block address & d0h read status register (2) yes no sr7 = 1 yes no sr3 = 0 yes sr4, sr5 = 1 v pp invalid error (1) command sequence error (1) no no sr5 = 0 erase error (1) end yes no sr1 = 0 erase to protected block error (1) yes erase_command ( blocktoerase ) { writetoflash (blocktoerase, 0x20) ; /*see note (2) */ writetoflash (blocktoerase, 0xd0) ; /* only a12-a20 are significannt */ /* memory enters read status state after the erase command */ } while (status_register.sr7== 0) ; do { status_register=readflash (blocktoerase) ; /* see note (2) */ /* e or g must be toggled*/ if (status_register.sr3==1) /*v pp invalid error */ error_handler ( ) ; if ( (status_register.sr4==1) && (status_register.sr5==1) ) /* command sequence error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; if ( (status_register.sr5==1) ) /* erase error */ error_handler ( ) ; }
m58lt128gst, m58lt128gsb 13 part numbering 87/98 figure 23. erase suspend & resume flowchart and pseudo code 1. the read status register command (write 70h) can be issued just before or just after the erase resume command. write 70h ai10116 read status register yes no sr7 = 1 yes no sr6 = 1 erase continues with bank in read status register mode write d0h read data from another block start write b0h erase complete write ffh read status register write ffh erase_suspend_command ( ) { writetoflash (bank_address, 0xb0) ; writetoflash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ do { status_register=readflash (bank_address) ; /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr6==0) /*erase completed */ { writetoflash (bank_address, 0xff) ; read_data ( ) ; /*read data from another block*/ /*the device returns to read array (as if program/erase suspend was not issued).*/ } else { writetoflash (bank_address, 0xff) ; read_program_data ( ); /*read or program data from another address*/ writetoflash (bank_address, 0xd0) ; /*write 0xd0 to resume erase*/ writetoflash (bank_address, 0x70) ; /*read status register to check if erase has completed */ } } write 70h (1)
13 part numbering m58lt128gst, m58lt128gsb 88/98 figure 24. protection register program flowchart and pseudo code write c0h (3) ai06177b start write address & data read status register (3) yes no sr7 = 1 yes no sr3 = 0 no sr4 = 0 v pp invalid error (1, 2) program error (1, 2) protection_register_program_command (addresstoprogram, datatoprogram) {: writetoflash (addresstoprogram, 0xc0) ; /*see note (3) */ do { status_register=readflash (addresstoprogram) ; /* see note (3) */ /* e or g must be toggled*/ } while (status_register.sr7== 0) ; if (status_register.sr3==1) /*vpp invalid error */ error_handler ( ) ; yes end yes no sr1 = 0 program to protected block error (1, 2) writetoflash (addresstoprogram, datatoprogram) ; /*memory enters read status state after the program command*/ if (status_register.sr4==1) /*program error */ error_handler ( ) ; if (status_register.sr1==1) /*program to protect block error */ error_handler ( ) ; }
m58lt128gst, m58lt128gsb 13 part numbering 89/98 figure 25. buffer enhanced factory program flowchart and pseudo code 1. for how to check the targeted block protection status, refer to the application note concerni ng the device security features. write 80h to address wa1 ai10658 start write d0h to address wa1 write ffffh to address = not wa1 read status register sr7 = 0 no no sr0 = 0 yes read status register sr3 and sr1for errors exit write pdx address wa1 increment count x = x + 1 initialize count x = 0 x = 32 yes read status register last data? yes read status register sr7 = 1 yes full status register check end yes sr4 = 1 no no no no setup phase program and verify phase exit phase buffer_enhanced_factory_program_command (start_address, dataflow[]) { verifytargeted block protection status if block protected return device to read mode writetoflash (start_address, 0x80) ; writetoflash (start_address, 0xd0) ; do { do { status_register = readflash (start_address); if (status_register.sr4==1) { /*error*/ if (status_register.sr3==1) error_handler ( ) ;/*v pp error */ if (status_register.sr1==1) error_handler ( ) ;/* locked block */ } while (status_register.sr7==1) x=0; /* initialize count */ do { writetoflash (start_address, dataflow[x]); x++; }while (x<32) do { status_register = readflash (start_address); }while (status_register.sr0==1) } while (not last data) writetoflash (another_block_address, ffffh) do { status_register = readflash (start_address) }while (status_register.sr7==0) full_status_register_check(); } verify block protection status protected block yes write ffffh to address wa1 read mode no
13 part numbering m58lt128gst, m58lt128gsb 90/98 appendix d command interface state tables table 46. command interface states - modify table, next state current ci state command input (1) read array (ffh) (2) program setup (10/40h) (3)(4) buffer program (e8h) (3)(4) block erase, setup (20h) (3)(4) befp setup (80h) erase confirm p/e resume, befp confirm(d0h) (3)(4) buffer program, program/ erase suspend (b0h) read status register (70h) clear status register (50h) (5) read electronic signature, read cfi query (90h, 98h) ready ready program setup buffer program setup erase setup befp setup ready lock/cr setup ready (lock error) ready ready (lock error) program setup program busy busy program busy program suspend program busy suspend program suspend program busy program suspend buffer program setup buffer program load 1 (give word count load (n-1)); buffer load 1 if n=0 go to buffer program confirm. else (n not =0) go to buffer program load 2 (data load) buffer load 2 buffer program confirm when count =0; else buffer program load 2 (note: buffer program will fail at this point if any block address is different from the first address) confirm ready (error) buffer program busy ready (error) busy buffer program busy buffer program suspend buffer program busy suspend buffer program suspend buffer program busy buffer program suspend erase setup ready (error) erase busy ready (error) busy erase busy erase suspend erase busy suspend erase suspend program in erase suspend buffer program setup in erase suspend erase suspend erase busy erase suspend program in erase suspend setup program busy in erase suspend busy program busy in erase suspend program suspend in erase suspend program busy in erase suspend suspend program suspend in erase suspend program busy in erase suspend program suspend in erase suspend
m58lt128gst, m58lt128gsb 13 part numbering 91/98 buffer program in erase suspend setup buffer program load 1 in erase suspend (give word count load (n-1 )); if n=0 go to buffer program confirm. else (n not =0) go to buffer program load 2 buffer load 1 buffer program load 2 in erase suspend (data load) buffer load 2 buffer program confirm in erase suspend when count =0; else bu ffer program load 2 in erase susp end (note: buffer program will f ail at this point if any block address is different from the first address) confirm ready (error) buffer program busy in erase suspend ready (error) busy buffer program busy in erase suspend buffer program suspend in erase suspend buffer program busy in erase suspend suspend buffer program suspend in erase suspend buffer program busy in erase suspend buffer program suspend in erase suspend lock/cr setup in erase suspend erase suspend (lock error) erase suspend erase suspend (lock error) buffer efp setup ready (error) befp busy ready (error) busy befp busy (6) 1. ci = command interface, cr = configuration register, befp = buffer enhanced factory program, p/e. c. = program/ erase controller. 2. at power-up, all banks are in read array mode. issuing a read array command to a busy bank, results in undetermined data output. 3. the two cycle command should be issued to the same bank address. 4. if the p/e.c. is active, both cycles are ignored. 5. the clear status register command clears the status regist er error bits except when the p/e.c. is busy or suspended. 6. befp is allowed only when status register bit sr0 is set to ?0?. befp is busy if block address is first befp address. any other commands are treated as data. current ci state command input (1) read array (ffh) (2) program setup (10/40h) (3)(4) buffer program (e8h) (3)(4) block erase, setup (20h) (3)(4) befp setup (80h) erase confirm p/e resume, befp confirm(d0h) (3)(4) buffer program, program/ erase suspend (b0h) read status register (70h) clear status register (50h) (5) read electronic signature, read cfi query (90h, 98h)
13 part numbering m58lt128gst, m58lt128gsb 92/98 table 47. command interface states - modify table, next output state current ci state command input (1)(2) read array (ffh) (3) program setup (10/ 40h) (4)(5) buffer program (e8h) block erase, setup (20h) (4)(5) befp setup (80h) erase confirm p/e resume, befp confirm (d0h) (4)(5) program/ erase suspend (b0h) read status register (70h) clear status register (50h) read electronic signature, read cfi query (90h, 98h) program setup status register erase setup program in erase suspend befp setup befp busy buffer program setup buffer program load 1 buffer program load 2 buffer program confirm buffer program setup in erase suspend buffer program load 1 in erase suspend buffer program load 2 in erase suspend buffer program confirm in erase suspend lock/cr setup lock/cr setup in erase suspend ready array status register output unchanged status register output unchanged electronic signature/ cfi program busy erase busy buffer program busy program/erase suspend buffer program suspend program busy in erase suspend buffer program busy in erase suspend program suspend in erase suspend buffer program suspend in erase suspend
m58lt128gst, m58lt128gsb 13 part numbering 93/98 table 48. command interface states - lock table, next state 1. the output state shows the type of data that appears at the outputs if the bank address is the same as the command address. a bank can be placed in read array, read status register, read electronic signature or read cfi mode, depending on the command issued. each bank remains in its last output state until a new command is issued to that bank. the next state does not depend on the bank output state. 2. ci = command interface, cr = configuration register, befp = buffer enhanced factory program, p/e. c. = program/ erase controller. 3. at power-up, all banks are in read array mode. issuing a read array command to a busy bank, results in undetermined data output. 4. the two cycle command should be issued to the same bank address. 5. if the p/e.c. is active, both cycles are ignored. current ci state command input (1)(2) lock/cr setup(60h) (2) set cr confirm (03h) block address (wa0) (xxxxh) (3) illegal command (4) wsm operation completed ready lock/cr setup ready n/a lock/cr setup ready (lock error) ready ready (lock error) n/a program setup program busy n/a busy program busy ready suspend program suspend n/a buffer program setup buffer program load 1 (give word count load (n-1) n/a buffer load 1 buffer program load 2 (5) exit see note (5) n/a buffer load 2 buffer program confirm when count =0; else buffer program load 2 (note: buffer program will fail at this point if any block address is different from the first address) n/a confirm ready (error) n/a busy buffer program busy ready suspend buffer program suspend n/a erase setup ready (error) n/a busy erase busy ready suspend lock/cr setup in erase suspend erase suspend n/a program in erase suspend setup program busy in erase suspend n/a busy program busy in erase suspend erase suspend suspend program suspend in erase suspend n/a buffer program in erase suspend setup buffer program load 1 in erase suspend (give word count load (n-1)) buffer load 1 buffer program load 2 in erase suspend (6) exit see note (6) buffer load 2 buffer program confirm in erase suspend when count =0; else buffer program load 2 in erase suspend (note: buffer program will fail at this point if any block address is different from the first address) confirm ready (error) busy buffer program busy in erase suspend suspend buffer program suspend in erase suspend
13 part numbering m58lt128gst, m58lt128gsb 94/98 lock/cr setup in erase suspend erase suspend (lock error) erase suspend erase suspend (lock error) n/a befp setup ready (error) n/a busy befp busy (7) exit befp busy (7) n/a 1. ci = command interface, cr = configuration register, befp = buffer enhanced factory program, p/e. c. = program/ erase controller, wa0 = address in a block different from first befp address. 2. if the p/e.c. is active, both cycles are ignored. 3. befp exit when block address is different from first block address and data are ffffh. 4. illegal commands are those not defined in the command set. 5. if n=0 go to buffer program confirm. else (n 0) go to buffer program load 2 (data load). 6. if n=0 go to buffer program confirm in erase suspend. else (n 0) go to buffer program load 2 in erase suspend. 7. befp is allowed only when status register bit sr0 is set to ?0?. befp is busy if block address is first befp address. any other commands are treated as data. current ci state command input (1)(2) lock/cr setup(60h) (2) set cr confirm (03h) block address (wa0) (xxxxh) (3) illegal command (4) wsm operation completed
m58lt128gst, m58lt128gsb 13 part numbering 95/98 table 49. command interface states - lock table, next output state current ci state command input (1)(2) 1. the output state shows the type of data that appears at the outputs if the bank address is the same as the command address. a bank can be placed in read array, read status register, read electronic signature or read cfi mode, depending on the command issued. each bank remains in its last output state until a new command is issued to that bank. the next state does not depend on the bank's output state. lock/cr setup (60h) (3) set cr confirm (03h) befp exit (ffffh) (4) illegal command (5) wsm operation completed program setup status register output unchanged erase setup program in erase suspend befp setup befp busy buffer program setup buffer program load 1 buffer program load 2 buffer program confirm buffer program setup in erase suspend buffer program load 1 in erase suspend buffer program load 2 in erase suspend buffer program confirm in erase suspend lock/cr setup status register array status register lock/cr setup in erase suspend ready output unchanged array output unchanged program busy erase busy buffer program busy program/erase suspend buffer program suspend program busy in erase suspend buffer program busy in erase suspend program suspend in erase suspend buffer program suspend in erase suspend
13 part numbering m58lt128gst, m58lt128gsb 96/98 2. ci = command interface, cr = configuration register, befp = buffer enhanced factory program, p/e. c. = program/ erase controller, wa0 = address in a block different from first befp address. 3. if the p/e.c. is active, both cycles are ignored. 4. befp exit when block address is different from first block address and data are ffffh. 5. illegal commands are those not defined in the command set.
m58lt128gst, m58lt128gsb 14 revision history 97/98 14 revision history table 50. document revision history date version revision details 16-nov-2004 0.1 first issue. 10-dec-2004 0.2 asynchronous page read mode added in summary description , section 3: bus operations . figure 10: asynchronous page read ac waveforms updated and table 22: asynchronous read ac characteristics for t avqv1 . 17-jan-2004 0.3 wp and r pins removed from figure 1: logic diagram . wp removed from figure 15: write ac waveforms, write enable controlled and figure 16: write ac waveforms, chip enable controlled . 20-jun-2005 0.4 80ns speed class chagned into 85ns. du pins changed into nc in figure 2: tbga64 connections (top view through package) . t whqv removed from figure 15 , figure 16 . ta bl e 2 2 , ta bl e 2 3 and table 26 updated. ta bl e 2 4 updated; t whqv removed and t avwh , t elqv , t elkv , t ghwl , t whav , and t whax timings added. ta bl e 2 5 updated, t whqv removed, and t aveh , t ehax , t ehgl , t elkv , and t ghel added. 21-jun-2005 0.5 t ghtz added in table 22: asynchronous read ac characteristics and ta bl e 2 3 : synchronous read ac characteristics . 29-sep-2005 1.0 burst frequency chagned from 54 to 52mhz. 85ns speed class removed. t avqv1 changed to 25ns. v io maximum value updated in table 17: absolute maximum ratings . t avlh and t lllh updated in table 22: asynchronous read ac characteristics . t avkh , t elkh and t llkh updated in table 23: synchronous read ac characteristics . t avlh , t lllh and t ellh updated in table 24: write ac characteristics, write enable controlled and table 25: write ac characteristics, chip enable controlled .
m58lt128gst, m58lt128gsb 98/98 information furnished is believed to be accurate and reliable. however, stmicroelectronics assu mes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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